Freeman Zhong

A 1.0625

A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s.

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A single-channel, asynchronous successive-approximation (SA) ADC with improved feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SAR-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparators quantization delay, as the digital logic delay is eliminated. Measurement results of the 40 nm-CMOS SAR-ADC achieves a peak SNDR of 32.9 dB and 30.5 dB, at 1 GS/s and 1.25 GS/s, consuming 5.28 mW and 6.08 mW, leading to a FoM of 148 fJ/conv-step and 178 fJ/conv-step, respectively, in a core area less than 170 um by 85 um.

14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance amplifier (TIA) base analog front-end achieved 15 dB high-frequency boost with an on-chip compact passive inductor. The adaptation loop for the boost is decoupled from the decision feedback equalizer (DFE) adaptation by the use of a group delay algorithm. The DFE is a half-rate 1-tap unrolled design with only two total error latches for power and area reduction. A two-stage sense amplifier-based latch achieved sensitivity of 15 mV. The high-speed clock buffer uses a PMOS active inductor circuit with common-mode feedback to optimize the circuit performance. The transceiver achieves error-free operation at 28 Gbps with 34 dB channel loss, consumes the worst case power of 560 mW/lane, and fully complies with multiple standards and applications.

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS

A single channel, loop-unrolled, asynchronous successive approximation (SAR) ADC fabricated in 40nm CMOS is presented. Compared with a conventional SAR structure that exhibits significant delay in the digital feedback logic, the proposed 6b SAR-ADC employs a different comparator for each bit of conversion, with an asynchronous ripple clock generated after each quantization. With the sample rate limited only by the six delays of the C-DAC settling and comparator quantizations, the 40nm-CMOS SAR-ADC achieves a peak SNDR of 32.9dB and 30.5dB at 1GS/s and 1.25GS/s, respectively, consuming 5.28mW and 6.08mW in a core area less than 170um × 85um.

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

AC coupling in a transmission link is preferred and often required for the functioning of high speed transceivers. But at data rate of 1OGbps and beyond, both the external AC coupling and the conventional on-chip AC coupling approaches bring in heavy burden that pushes to the fundamental limits and are difficult to afford. This paper examines the AC-coupling methods for multi-Gb/s transceivers, and points out the impairments in the existing implementations. A hybrid structure offering both the signal-bump and the AC-capacitor functions under the stringent return-loss requirements of a 1OGb/s+ I/O is proposed and implemented in 65nm standard CMOS. A sizeable 5.1pF AC capacitor is measured with ultra low parasitic expense ratio of less than 120fF.

Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS

A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<;10-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at VDD=0.8V.

AC-coupling strategy for high-speed transceivers of 10Gbps and beyond

We investigate the prospect of low-jitter wide frequency range high-speed clocking implementation. A novel architecture features multi-LCVCO with mitigation of dormant VCO leakage current and capacitive modulation is proposed. The new scheme decouples the typical trade-offs between tuning-range, achievable speed and jitter-performances. It enables high frequency low jitter PLL design with sizable tuning range in nowadays highly leaky standard CMOS. A novel self calibration method is presented to seamlessly activate a proper VCO with a proper switched-tuning band to bias the PLL in its optimal operating point. Hence, design requirements for critical circuits including the VCO, the first divide-by-2 and the loop-filter are relaxed. The proposed scheme was implemented and validated in silicon.