Ameya R. Agnihotri

Recursive bisection placement: feng shui 5.0 implementation details

In this paper, we summarize circuit placement techniques and algorithms developed by the BLAC CAD research group; these have been integrated into our recursive bisection based placement tool feng shui. We also briefly describe current research interests.

Mixed block placement via fractional cut recursive bisection

Recursive bisection is a popular approach for large scale circuit placement problems, combining a high degree of scalability with good results. In this paper, we present a bisection-based approach for both standard cell and mixed block placement; in contrast to prior work, our horizontal cut lines are not restricted to row boundaries. This technique, which we refer to as a fractional cut, simplifies mixed block placement and also avoids a narrow region problem encountered in standard cell placement. Our implementation of these techniques in the placement tool Feng Shui 2.6 retains the speed and simplicity for which bisection is known, while making it competitive with leading methods on standard cell designs. On mixed block placement problems, we obtain substantial improvements over recently published work. Half perimeter wire lengths are reduced by 29% on average, compared to a flow based on Capo and Parquet; compared to mPG-ms, wire lengths are reduced by 26% on average.

Fast Analytic Placement using Minimum Cost Flow

Many current integrated circuits designs, such as those released for the ISPD2005 (Nam et al., 2005) placement contest, are extremely large and can contain a great deal of white space. These new placement problems are challenging; analytic placers perform well, but can suffer from high run times. In this paper, we present a new placement tool called Vaastu. Our approach combines continuous and discrete optimization techniques. We utilize network flows, which incorporate the more realistic half-perimeter wire length objective, to facilitate module spreading in conjunction with a log-sum-exponential function based analytic approach. Our approach obtains wire length results that are competitive with the best known results, but with much lower run times.

Large-Scale Circuit Placement

Modern computing systems contain staggering numbers of transistors and interconnecting wires, and blocks of widely varying size and shape. The placement problem is intractable for even small problems and simple metrics; heuristic methods, and in particular, multi-level formulations, are commonplace across the industry. In this chapter we survey modern techniques for circuit placement, with an emphasis on how placement interacts with logic synthesis and routing. Stability of placement methods is now a key concern: to allow timing closure it is essential that gate sizing, buffer insertion, and routing can be completed without large disruptions to the overall physical structure of a circuit. We also discuss fundamental aspects of computing circuits that have made the placement problem progressively more difficult — resulting in a recent shift toward “multi-core” microprocessors.We argue that this change is an extremely significant event, as it fundamentally changes how microprocessor design must be pursued.