K. Srihari

Mixed integer formulation to minimize makespan in a flow shop with batch processing machines

Batch processing machines are commonly used in wafer fabrication, kilns, and chambers used for environmental stress screening (ESS). This paper proposes two models to schedule batches of jobs on two machines in a flow shop. A set of jobs with known processing times and sizes has to be grouped, to form batches, in order to be processed on the batch processing machines. The jobs are nonidentical in size. The processing time of a batch is the longest processing time of all the jobs in that batch. Mixed integer formulations are proposed for the flow shop problem when the buffer capacity is unlimited or zero. Numerical examples are presented to demonstrate the application of our model.

A review of petri-net applications in manufacturing

Petri-nets (PNs) can model concurrent and synchronous activities in a manufacturing system at various levels of abstraction. They have been used for modelling manufacturing systems, knowledge representation on the shop floor, process-planning applications, decisionsupport tasks, etc. PNs are being used in a growing variety of application areas. This paper focuses on PN applications in manufacturing. A comprehensive review of research is provided. The paper also describes the design and application of PNs in the modelling of a manufacturing cell, the representation of the working of the cell at various levels of abstraction, and the inferences that can be drawn through PN use. Ideas for future research are presented.

An expert system methodology for aircraft-gate assignment

Abstract The aircraft-gate assignment problem is a significant concern in airline operations. This paper addresses the use of knowledge based expert systems to help solve the aircraft-gate assignment problem. The problem is described and the factors that need to be considered in aircraft-gate assignment are identified and delineated. The expert systems architecture is presented and its working is described.

A knowledge based aircraft-gate assignment advisor

Abstract An expert system based solution to the aircraft-gate assignment problem is discussed. The prototype system developed works as a planning tool. It assists in the strategic planning of schedules and with projected aircraft-gate assignments.

A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through -silicon - vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

Voids in thermal interface material layers and their effect on thermal performance

One of the key challenges in the thermal management of microelectronic devices is interfaces such as those between the chip and heat spreader and between the heat spreader and heat sink or cold plate. Typically, thermal interfaces are filled with materials such as thermal adhesives and greases. Interface materials reduce the contact resistance between the mating heat generating and heat sinking units by filling voids and grooves created by the nonsmooth surface topography of the mating surfaces, thus improving surface contact and the conduction of heat across the interface. With shrinking thermal budgets, the role of these layers in the cooling of microelectronic devices has become more critical. Voids in thermal interface material (TIM) layers may be trapped during the flow of the TIM during assembly, due to outgassing during the curing process, or due to insufficient volume. The negative effect of such voids on the thermal resistance of a TIM layer can be devastating. In applications where the TIM performs the function of a structural adhesive, voids may negatively affect the adhesion strength and reliability of the TIM layer. In this work, the effect of voids and their characteristics on the thermal performance of thermal interface adhesive layers is reported.

Accelerating the effects of aging on the reliability of lead free solder joints in a quantitative fashion

The properties of lead free solder joints continue to change over a very long period of time in service before the microstructure becomes stable. The quantitative assessment of long term service life by accelerated testing invariably misses this significant effect, and may thus end up seriously misleading. The long term goal of the present work is to establish a protocol for preconditioning of lead free solder joints before thermal cycling or mechanical testing. For this purpose, the state of a solder joint at any given time was characterized in terms of three different room temperature properties, shear strength, shear fatigue resistance, and micro hardness. These properties were measured before and after aging for different lengths of time at different temperatures. Three common lead free alloys were selected for the present study: 98.5Sn-1.0Ag-0.5Cu (SAC105), 96.5Sn-3.0Ag-0.5Cu (SAC305), and 95.5Sn-4.0Ag-0.5Cu (SAC405). The present study did not address effects of solder volume, pad size, pad finish or reflow profile, focusing on 30 mil (760µm) diameter solder spheres reflowed onto solder mask defined OSP coated Cu pads with a typical lead free profile. Isothermal aging was conducted for up to 3,000 hours at temperatures of 70°C, 100°C, and 125°C respectively. As expected, the resulting room temperature properties all decreased with aging time, and faster so for higher aging temperatures. Some of the acceleration factors extracted for the evolution of the individual properties did, however, differ greatly for a given alloy. The only way to establish the same microstructure, and thus the same combination of properties, faster by annealing at a higher temperature is thus to fully stabilize it. This takes thousands of hours even at 125°C, i.e. it is not practical for real assemblies.

A simulation based approach for dock allocation in a food distribution center

This research endeavor focused on the warehouse receiving process at a large food distribution center, which comprises of trucks with goods reaching the destination warehouse, unloading and finally putting away the contents to the specific aisles. Discrete event simulation was used to model the current system¿s functioning and to identify operational inefficiencies which were quantified through a detailed value stream mapping exercise. Inspired by `lean¿ philosophy, a dock allocation algorithm was designed to take into account the relationship between the dock location and the destination aisle to `optimally¿ assign the trucks to the docks. After validating the baseline, new scenarios incorporating the allocation algorithm were tested. Two of the scenarios showed an average reduction of 30% in daily travel distance for the `put-away¿ personnel. The simulation model also helped visualize the benefits that would accrue through the use of lean principles to reduce the non-value added time in warehouse operations.

Assessment of PCB pad cratering resistance by joint level testing

Cracking of the laminate under the solder connect pads, known as pad craters, is a reliability issue related to mechanical stresses generated from either mechanical or thermal loading. The current study aims to establish a mechanistic understanding of pad cratering through the use of joint-level testing techniques. Both strength and cyclic loading lifetime are considered, and the results indicate that these two loading modes are not correlated. The individual crack paths within a crater are found to differ with laminate material, glass style (if any), and micro-via details. Various degradation mechanisms are found to have a significant effect on this failure mode with both thermal and moisture exposure showing decreased laminate performance. Finally, the relationship between joint-level testing is compared to the performance in board level drop test. Here we see that joint-level testing is far more general, in terms of qualifying the robustness of the laminate.

Effects of assembly process variables on voiding at a thermal interface

Too often, the effects of assembly process parameters are not sufficiently accounted for in the optimization of thermal interface performance. This becomes increasingly critical as demands on this performance continue to grow and alternative processes are developed. Notably, stencil printing is proving a competitive alternative to the traditional dispensing of thermal interface materials (TIMs), with potentially significant gains in units processed per hour (UPH) for some applications. The two techniques may, however, pose quite different challenges in terms of material flow, the resulting filler particle distribution and the risk of air bubble entrapment. Another part of the adhesive attachment process certain to affect void formation and growth, as well as possibly filler particle distribution, is the final cure. In addition, voids may severely reduce assembly robustness and reliability. The present work offers a discussion and a first case study to identify and illustrate voiding mechanisms for a particular TIM between a heat spreader and the back of a flip chip. Pronounced differences were observed between stencil printing and dispensing in terms of initial void formation, apparently related to the specific properties of the material. Measurements of the effects of heat ramp rate and peak temperature showed the subsequent evolution and final void size distribution to be determined by the initial part of the cure profile up to the material gelling temperature.