Amin Nassar

Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm

This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.

A quality guaranteed robust image watermarking optimization with Artificial Bee Colony

Achieving robustness with a limited distortion level is a challenging design problem for watermarking systems in multimedia applications with a guaranteed quality requirement. In this paper, we provide an intelligent system for watermarking through incorporating a meta-heuristic technique along with an embedding method to achieve an optimized performance. The optimization objective is to provide the maximum possible robustness without exceeding a predetermined distortion limit. Hence, the quality level of the watermarking method could be guaranteed through that constraint optimization. A new fitness function is defined to provide the required convergence toward the optimum solution for the defined optimization problem. The fitness function is based on dividing its applied solution population into two groups, where each group is ranked according to a different objective. Thus, the multi-objectives in the problem are decoupled and solved through two single-objective sub-problems. Unlike existing watermarking optimization techniques, the proposed work does not require weighting factors. To illustrate the effectiveness of the proposed approach, we employ a recent watermarking technique, and then use it as the embedding method to be optimized. The Artificial Bee Colony is selected as the meta-heuristic optimization method in which the proposed fitness function is used. Experimental results show that the imposed quality constraint is satisfied, and that the proposed method provides enhanced robustness under different attacks for various quality thresholds. The presented approach offers a robust solution that can be applied to numerous multimedia applications such as film industry, intelligent surveillance and security systems.

Power-Efficient Clock/Data Distribution Technique for Polyphase Comb Filter in Digital Receivers

A power-efficient clock/data distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed with respect to the decimation factor. Both proposed and conventional comb filters are implemented using Xilinx Spartan3 low-power field-programmable gate array family. The implementation results show that applying the proposed technique reduces the dynamic power consumption of the second- and third-order polyphase comb filters up to 62.87% and 57.6%, respectively, depending on the decimation factor and the number of quantizer bits. For a particular power consumption, a higher input sampling rate can be utilized by applying the proposed technique. Consequently, the signal-to-noise ratio of a second-order SigmaDelta modulator is increased using second- and third-order modified filters by 21.6 and 20.5 dB, respectively, depending on the decimation factor and the number of quantizer bits.

New blind equalization technique for Constant Modulus Algorithm (CMA)

Equalization plays an important role for the communication system receiver to correctly recover the symbol send by the transmitter, where the received signals may contain additive noise and intersymbol interference (ISI). Blind equalization is a technique of many equalization techniques at which the transmitted symbols over a communication channel can be recovered without the aid of training sequences, recently blind equalizers have a wide range of research interest since they do not require training sequence and extra bandwidth, but the main weaknesses of these approaches are their high computational complexity and slow adaptation, so different algorithms are presented to avoid this nature. The most popular blind algorithm which has a wide acceptance is the Constant Modulus Algorithm (CMA). The performance of CMA suffers from slow convergence rate or adaptation which corresponds to various transmission delays especially in wireless communication systems, which require higher speed and lower bandwidth. This paper introduces a new blind equalization technique, the Exponentially Weighted Step-size Recursive Least Squares Constant Modulus Algorithm (EXP-RLS-CMA), based upon the combination between the Exponentially Weighted Step-size Recursive Least Squares (EXP-RLS) algorithm and the Constant Modulus Algorithm (CMA), by providing several assumptions to obtain faster convergence rate to an optimal delay where the Mean Squared Error (MSE) is minimum, and so this selected algorithm can be implemented in digital system to improve the receiver performance. Simulations are presented to show the excellence of this technique, and the main parameters of concern to evaluate the performance are, the rate of convergence, the mean square error (MSE), and the average error versus different signal-to-noise ratios.

Quality metric-based fitness function for robust watermarking optimisation with Bees algorithm

The design of a robust watermarking technique has been always suffering from the conflict between the watermark robustness and the quality of the watermarked image. In this study, the embedding strength parameters for per-block image watermarking in the discrete cosine transform (DCT) domain are optimised. A fitness function is proposed to best suit the optimisation problem. The optimum solution is selected based on the quality and the robustness achieved using that solution. For a given image block, the peak-signal-to-noise ratio (PSNR) is used as a quality metric to measure the imperceptibility for the watermarked block. However, the robustness cannot be measured for a single watermark bit using traditional metrics. The proposed method uses the PSNR quality metric to indicate the degree of robustness. Hence, optimum embedding in terms of quality and robustness can be achieved. To demonstrate the effectiveness of the proposed approach, a recent watermarking technique is modified, and then used as the embedding method to be optimised. The Bees algorithm is selected as the optimisation method and the proposed fitness function is applied. Experimental results show that the proposed method provides enhanced imperceptibility and robustness under different attacks.

High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm

This paper presents a new processor array architecture for scalable radix 2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by C. Koc. Also, the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance-in terms of area and speed-and lower power consumption than the previous architecture extracted by Ç. Koç.

New processor array architecture for scalable radix 2 Montgomery modular multiplication algorithm

This paper presents a new processor array architecture for scalable radix2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by Ç . Koç, and also the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance - in terms of area and speed - than the previous architecture extracted by Ç. Koç.

Towards the implementation of Multi-band Multi-standard Software-Defined Radio using Dynamic Partial Reconfiguration

Summary The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine-grained block level, in implementing a baseband physical layer processing module for software-defined radio (SDR) chain that supports 3G, long-term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run-time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5-LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long-term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.

Power efficient polyphase comb decimation filters for ΣΔ modulators in multi-rate digital receivers

In multi-rate digital receivers, Analog to Digital Converter (ADC) mostly works at a fixed sampling rate. Subsequently, a Sample Rate Conversion (SRC) process should be executed after the ADC to extract the desired baud rate. A polyphase decomposition comb filter is widely used as a first decimation stage in SRC circuit. In this paper, a power efficient clock/data distribution technique for the input registers of the polyphase decomposition comb filter is introduced. A general form of the proposed technique is developed with respect to the filter decimation factor. An FPGA implementation for both modified and conventional polyphase comb filters is presented using Xilinx Spartan3 low power FPGA family. Implementation results show that, the proposed technique significantly reduces the overall dynamic power consumption of the polyphase comb filter up to 51.3 % and 47%, for second and third order filters respectively, depending on the decimation factor. For particular power consumption, higher input sampling frequencies is achieved by applying the proposed technique. That, in turns, improves the SNR of a second order ΣΔ modulator up to 14.82 dB and 12.4 dB, using second and third order modified filters, respectively, depending on the decimation factor.

Power efficient polyphase decomposition comb decimation filter in multi-rate telecommunication receivers

A power efficient polyphase decomposition comb filter with a novel clock distribution algorithm for its memory elements is presented. The proposed algorithm results in a significant reduction in the dynamic power consumption, comparing with the conventional polyphase decomposition comb filter that is widely used as a first stage of decimation process in sample rate conversion for multi-rate telecommunication receivers. A general form of the proposed clock distribution algorithm is presented with respect to the decimation factor of the polyphase comb filter. It is shown that, using the proposed clock distribution algorithm reduces the dynamic power consumption of the memory elements for a second order polyphase comb filter up to 33.33%, 40%, 60.32%, and 71.37%. As well as, reducing the dynamic power consumption of the memory elements for a third order polyphase comb filter up to 25%, 33.33%, 54.29%, and 67.41% for decimation factors 2, 4, 8, and 16 respectively.