Hassan Mostafa

A Modified CMOS Realization of the Operational Transresistance Amplifier (OTRA)

A modified CMOS realization of the operational transresistance amplifier (OTRA) is presented. A fair comparison with Salama and Soliman OTRA [1] shows that the modified OTRA provides better performance in all parameters. The OTRA is suitable for analog VLSI applications since it does not suffer from constant gain bandwidth product. Hence, it can exhibit wide bandwidth at high gain values. Moreover, an OTRA based variable gain amplifier (VGA) is introduced. A detailed analysis taking the effect of the finite transresistance gain in consideration is provided. Index Terms – CMOS operational transresistance amplifier, analog VLSI applications, variable gain amplifier, wireless communications,

Environmental life cycle assessment and techno-economic analysis of triboelectric nanogenerators

As the world economy grows and industrialization of the developing countries increases, the demand for energy continues to rise. Triboelectric nanogenerators (TENGs) have been touted as having great potential for low-carbon, non-fossil fuel energy generation. Mechanical energies from, amongst others, body motion, vibration, wind and waves are captured and converted by TENGs to harvest electricity, thereby minimizing global fossil fuel consumption. However, only by ascertaining performance efficiency along with low material and manufacturing costs as well as a favorable environmental profile in comparison with other energy harvesting technologies, can the true potential of TENGs be established. This paper presents a detailed techno-economic lifecycle assessment of two representative examples of TENG modules, one with a high performance efficiency (Module A) and the other with a lower efficiency (Module B) both fabricated using low-cost materials. The results are discussed across a number of sustainability metrics in the context of other energy harvesting technologies, notably photovoltaics. Module A possesses a better environmental profile, lower cost of production, lower CO2 emissions and shorter energy payback period (EPBP) compared to Module B. However, the environmental profile of Module B is slightly degraded due to the higher content of acrylic in its architecture and higher electrical energy consumption during fabrication. The end of life scenario of acrylic is environmentally viable given its recyclability and reuse potential and it does not generate toxic gases that are harmful to humans and the environment during combustion processes due to its stability during exposure to ultraviolet radiation. Despite the adoption of a less optimum laboratory manufacturing route, TENG modules generally have a better environmental profile than commercialized Si based and organic solar cells, but Module B has a slightly higher energy payback period than PV technology based on perovskite-structured methyl ammonium lead iodide. Overall, we recommend that future research into TENGs should focus on improving system performance, material optimization and more importantly improving their lifespan to realize their full potential.

Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs)

Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz.

A Novel Nondestructive Read/Write Circuit for Memristor-Based Memory Arrays

Emerging nonvolatile universal memory technology is vital for providing the huge storage capabilities, which is needed for nanocomputing facilities. Memristor, which is recently discovered and known as the missing fourth circuit element, is a potential candidate for the next-generation memory. Memristor has received extra attention in the last few years. To support this effort, this paper presents a novel read/write circuit that facilitates the reading and writing operation of the Memristor device as a memory element. The advantages of the proposed read/write circuit are threefold. First, the proposed circuit has a nondestructive successive reading cycle capability. Second, it occupies less die area. Finally, the proposed read/write circuit offers a significant improvement in power consumption and delay time compared with other read/write circuits.

Process Variation Aware Design of Multi-Valued Spintronic Memristor-Based Memory Arrays

The missing fourth passive element, predicted by L. Chua and denoted by memristor, has recently been in the research focus since its titanium dioxide thin film realization is reported by HP. Following that, the spintronic memristor, which is based on the magnetic tunneling junction, is presented as an alternative to the thin film memristor. The nano-scale geometry size of the memristor makes it hard to control its dimensions due to the process variation resulting from the fabrication process. This process variation results in yield degradation in the spintronic memristor-based memory arrays. This yield degradation is more significant when the spintronic memristor is utilized as a multi-valued memory elements. In this paper, the impact of the process variation on the spintronic memristor-based memory yield is discussed for the 1-bit, 2-bit, and n-bit memory element. Moreover, two approaches are introduced to enhance the memory yield.

Priority-select arbiter: An efficient round-robin arbiter

Round robin arbiter (RRA) is a critical block in nowadays designs. It is widely found in System-on-chips and Network-on-chips. The need of an efficient RRA has increased extensively as it is a limiting performance block. In this paper, we deliver a comparative review between different RRA architectures found in literature. We also propose a novel efficient RRA architecture. The FPGA implementation results of the previous RRA architectures and our proposed one are given, that show the improvements of the proposed RRA.

Micro-scale variation-tolerant exponential tracking energy harvesting system for wireless sensor networks

Self-powered stand-alone electronic systems, targeting low power applications, are the future of power management. In wireless sensor networks (WSNs) and implantable devices, battery replacement is expensive and power management of these systems is essential. Energy harvesting is considered one of the main power management methods that scavenge energy from the ambient resources that are available and abundant. They take the advantage of minimizing the maintenance costs as well as saving area (Penella-Lopez and Gasulla-Forner, 2011 1]). This paper presents a new tracking technique for maximum power harvesting of solar energy using a micro-scale photovoltaic cell. The new design is based on the analytical derivation of the system equations. The power converter used is a tree topology charge pump, the control circuit is a low frequency voltage controlled oscillator (VCO), and the energy storage element is an output super-capacitor. The system is designed using TSMC 65nm technology node. Typical power efficiency of the proposed circuit reaches 63% where the proposed design is targeting indoors and outdoors light intensities at zero load condition. The maximum power consumption of the harvester reaches 170 µ W .

Statistical yield improvement under process variations of multi-valued memristor-based memories

Abstract Memristor, the missing fourth element predicted by L. Chua, has recently been in the research focus since HP Lab reported the first TiO 2 thin film memristor realization. The nano-scale geometry size of the memristor makes it difficult to control its dimensions due to the process variation incurred in the fabrication process. This process variation results in yield degradation in the memristor-based memories. This yield degradation is more severe when the memristor device is used as a multi-valued memory element. In this paper, the impact of the process variation on the memristor-based memory yield is investigated for the 1-bit, 2-bit, and n-bit memristor memory element. In addition, two approaches are proposed to improve the memory yield. Therefore, the main objective of this work is to introduce a statistical yield simulation flow to calculate the memory statistical yield under process variations and investigate the effect of different design knobs on this statistical yield regardless of the memristor models and the process variation models used. Simulation results reveal that for 1-bit memristor-based memories, the nominal write voltage should be increased by 30% and the nominal threshold value (i.e., the midway memristance value between the memristor ON resistance and the memristor OFF resistance) should be increased by 65% to achieve the maximum yield. Finally, the paper lists the minimum memristor size that should be used to achieve a 99.9% memory yield for n-bit memories. These results show how the process variation imposes limitations on the minimum memristor device size when multi-valued memories are to be designed.

A new highly-linear highly-sensitive differential voltage-to-time converter circuit in CMOS 65nm technology

Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital word. In this paper, a novel design of a differential VTC circuit is proposed which reports wider dynamic range and higher sensitivity than previously published VTC circuits in TSMC 65nm CMOS technology, with a supply voltage of 1.2V. This new VTC circuit operates with no sample and hold circuit for analog input frequencies up to 2.5 GHz with a linearity error of 3%.

Comparative review of NoCs in the context of ASICs and FPGAs

Network-on-Chip (NoC) is an emerging solution for interconnect problems for both ASICs and FPGAs nowadays. In this paper, we deliver a comparative review between ASIC-based and FPGA-based NoCs. An exploration of design tradeoffs for different NoC design parameters is also given. We also propose an evaluation methodology and design recommendations for various design parameters for both ASIC and FPGA oriented NoCs. These design recommendations help in selecting the optimum design parameters according to the requirements of the application used.