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Dive into the research topics where Amir R. B. Behrouzian is active.

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Featured researches published by Amir R. B. Behrouzian.


international conference on embedded computer systems architectures modeling and simulation | 2015

Multi-Constraint multi-processor Resource Allocation

Amir R. B. Behrouzian; Dip Goswami; Twan Basten; Marc Geilen; Hadi Alizadeh Ara

This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained streaming applications and multiple latency-constrained feedback control applications onto a multi-processor platform running under a Time-Division Multiple-Access (TDMA) policy. The main objective of the proposed method is to reduce resource usage while meeting constraints from both these two domains (i.e., throughput and latency constraints). We show by experiments that the overall resource usage for this mapping problem can be reduced by distributing the allocated resource (i.e., TDMA slots) to the control applications over the TDMA wheel instead of allocating consecutive slots.


ACM Sigbed Review | 2017

xCPS: a tool to explore cyber physical systems

S Shreya Adyanthaya; Hadi Alizadeh Ara; Jp Joao Bastos; Amir R. B. Behrouzian; Róbinson Medina Sánchez; Joost van Pinxten; Bram van der Sanden; Umar Waqas; Twan Basten; Henk Corporaal; Raymond Frijns; Marc Geilen; Dip Goswami; Martijn Hendriks; Sander Sander Stuijk; Ma Michel Reniers; Jeroen Voeten

Cyber-Physical Systems (CPS) play an important role in the modern high-tech industry. Designing such systems is an especially challenging task due to the multi-disciplinary nature of these systems, and the range of abstraction levels involved. To facilitate hands-on experience with such systems, we develop a cyber-physical platform that aids in both research and education on CPS. This paper describes this platform, which contains all typical CPS components. The platform is used in various research and education projects for bachelor, master, and PhD students. We discuss the platform and illustrate its use with a number of projects and the educational opportunities they provide.


international symposium on industrial embedded systems | 2016

Tight temporal bounds for dataflow applications mapped onto shared resources

Hadi Alizadeh Ara; Marc Geilen; Twan Basten; Amir R. B. Behrouzian; Martijn Hendriks; Dip Goswami

We present an analysis method that provides tight temporal bounds for applications modeled by Synchronous Dataflow Graphs and mapped to shared resources. We consider the resource sharing effects on the temporal behaviour of the application by embedding worst case resource availability curves in the symbolic simulation of the application graph. Symbolic simulation of the application results in a (max, +) characterization matrix. This matrix specifies a set of recursive linear equations in (max, +) algebra that bound the worst case execution of the application. We obtain tighter temporal bounds on the completion times of tasks than state of the art analysis. This is achieved by improving the response times of the tasks by identifying possible consecutive task executions on the resources. This enables us to use accumulated response times which are less pessimistic. Applying the new approach to real-life applications gives significant improvements over the bounds compared to state of the art.


international symposium on industrial embedded systems | 2016

Sample-drop firmness analysis of TDMA-scheduled control applications

Amir R. B. Behrouzian; Dip Goswami; Mcw Marc Geilen; Martijn Hendriks; H. Alizadeh Ara; E. P. van Horssen; Wpmh Maurice Heemels; Twan Basten

This paper proposes methods for verification of (m, k)-firmness properties of control applications running on a shared TDMA-scheduled processor. We particularly consider dropped samples arising from processor sharing. Based on the available processor budget for any sample that is ready for execution, the Finite-Point (FP) method is proposed for quantification of the maximum number of dropped samples. The FP method is further generalized using a timed automata based model to consider the variation in the period of samples. The UPPAAL tool is used to validate and verify the timed automata based model. The FP method gives an exact bound on the number of dropped samples, whereas the timed-automata analysis provides a conservative bound. The methods are evaluated considering a realistic case study. Scalability analysis of the methods shows acceptable verification times for different sets of parameters.


real time networks and systems | 2018

Throughput-Buffering Trade-Off Analysis for Scenario-Aware Dataflow Models

Hadi Alizadeh Ara; Marc Geilen; Amir R. B. Behrouzian; Twan Basten

In multi-media applications, buffers represent storage spaces that are used to store the data communicated between different tasks in the application, and throughput refers to the rate at which output data is produced by the application. The capacities of the buffers influence the throughput, by altering the waiting times for tasks that need to read or write data from or to the buffers. The buffers are realized using memory. To minimize the memory usage, we look for algorithms to compute the minimal capacity requirements for buffers to execute an application under a given throughput constraint. Synchronous dataflow (SDF) is a common formalism used to model applications in such algorithms. SDF however, is not suitable to describe todays dynamic applications, as it cannot express task variations. Finite-State-Machine Scenario-Aware Dataflow (FSM-SADF) is an extension of SDF that allows for not only task variations, but also structural variations, making it suitable for a wide range of dynamic applications. This paper provides the first throughput-bufering trade-of analysis for FSM-SADF models. The analysis provides the Pareto space of throughput and storage space trade-offs. The trade-off analysis is done by a guided Design Space Exploration (DSE) that cuts-off the exploration on non-critical buffers. The core of such a DSE is an FSM-SADF throughput analysis that, given the capacity of every buffer, obtains the throughput, as well as the critical buffers. We demonstrate the feasibility of our analysis with a number of examples.


ACM Transactions in Embedded Computing Systems | 2018

Scalable analysis for multi-scale dataflow models

Hadi Alizadeh Ara; Amir R. B. Behrouzian; Martijn Hendriks; Marc Geilen; Dip Goswami; Twan Basten

Multi-scale dataflow models have actors acting at multiple granularity levels, e.g., a dataflow model of a video processing application with operations on frame, line, and pixel level. The state of the art timing analysis methods for both static and dynamic dataflow types aggregate the behaviours across all granularity levels into one, often large iteration, which is repeated without exploiting the structure within such an iteration. This poses scalability issues to dataflow analysis, because behaviour of the large iteration is analysed by some form of simulation that involves a large number of actor firings. We take a fresh perspective of what is happening inside the large iteration. We take advantage of the fact that the iteration is a sequence of smaller behaviours, each captured in a scenario, that are typically repeated many times. We use the (max ,+) linear model of dataflow to represent each of the scenarios with a matrix. This allows a compositional worst-case throughput analysis of the repeated scenarios by raising the matrices to the power of the number of repetitions, which scales logarithmically with the number of repetitions, whereas the existing throughput analysis scales linearly. We moreover provide the first exact worst-case latency analysis for scenario-aware dataflow. This compositional latency analysis also scales logarithmically when applied to multi-scale dataflow models. We apply our new throughput and latency analysis to several realistic applications. The results confirm that our approach provides a fast and accurate analysis.


international conference on application of concurrency to system design | 2016

Checking Metric Temporal Logic with TRACE

Martijn Hendriks; Marc Geilen; Amir R. B. Behrouzian; Twan Basten; Hadi Alizadeh; Dip Goswami

Execution traces, time-stamped sequences of events, provide a general, domain-independent, view on the behavior of systems. They enable analysis of metrics such as latency, pipeline depth and throughput. Often, however, it is not clear what such metrics exactly mean and ad hoc methods are used to compute them. Metric Temporal Logic (MTL) can be used to address this issue: it enables the formal specification of quantitative properties on execution traces. We thus have added an MTL checking capability to the TRACE tool, which is a tool for viewing and analyzing execution traces [1]. We use a recursive memoization algorithm that generates concise explanations of the truth value of the given MTL formula. These explanations can be visualized in the TRACE viewer to aid interpretation by the user.


workshop on embedded and cyber-physical systems education | 2015

xCPS: A tool to eXplore Cyber Physical Systems

S Shreya Adyanthaya; Hadi Alizadeh Ara; Jp Joao Bastos; Amir R. B. Behrouzian; Róbinson Medina Sánchez; Joost van Pinxten; Bram van der Sanden; Umar Waqas; Twan Basten; Henk Corporaal; Raymond Frijns; Marc Geilen; Dip Goswami; Sander Sander Stuijk; Ma Michel Reniers; Jeroen Voeten


real time technology and applications symposium | 2018

Firmness Analysis of Real-Time Applications Under Static-Priority Preemptive Scheduling

Amir R. B. Behrouzian; Dip Goswami; Twan Basten; Marc Geilen; Hadi Alizadeh; Martijn Hendriks


digital systems design | 2018

Compositional Dataflow Modelling for Cyclo-Static Applications

Hadi Alizadeh Ara; Marc Geilen; Amir R. B. Behrouzian; Twan Basten; Dip Goswami

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Twan Basten

Eindhoven University of Technology

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Dip Goswami

Eindhoven University of Technology

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Marc Geilen

Eindhoven University of Technology

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Hadi Alizadeh Ara

Eindhoven University of Technology

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Martijn Hendriks

Radboud University Nijmegen

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Bram van der Sanden

Eindhoven University of Technology

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Hadi Alizadeh

Eindhoven University of Technology

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Henk Corporaal

Eindhoven University of Technology

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Jeroen Voeten

Eindhoven University of Technology

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Joost van Pinxten

Eindhoven University of Technology

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