Amirali Amirsoleimani

Optimized implementation of memristor-based full adder by material implication logic

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.

Memristor-based linear feedback shift register based on material implication logic

Memristor as an emerging history dependent nanometer scaled element will play an important role in future nanoelectronic computing technologies. Some pure and hybrid memristor-based implementation techniques have been proposed in recent years. Material implication logic is one of the significant areas for memristor-based logic implementation. In this paper a memristor-based linear feedback shift register is implemented based on material implication logic. It is implemented by 8 memristors which is considerably used less area in comparison with conventional CMOS-based peers. Also the proposed memristor-based LFSR circuit needs 55 computational steps for generating a 4-bits number.

Brain-inspired pattern classification with memristive neural network using the Hodgkin-Huxley neuron

Recent findings about using memristor devices to mimic biological synapses in neuromorphic systems open a new vision in neuroscience. Ultra-dense learning architectures can be implemented through the Spike-Timing-Dependent-Plasticity (STDP) mechanism by exploiting these nanoscale nonvolatile devices. In this paper, a Spiking Neural Network (SNN) that uses biologically plausible mechanisms is implemented. The proposed SNN relies on Hodgkin-Huxley neurons and memristor-based synapses to implement a bio-inspired neuromorphic platform. The behavior of the proposed SNN and its learning mechanism are discussed, and test results are provided to show the effectiveness of the proposed design for pattern classification applications.

STDP-based unsupervised learning of memristive spiking neural network by Morris-Lecar model

These days, there is an increasing interest in implementation of spiking neural systems that can be used to perform complex computations or solve pattern recognition tasks like mammalian neocortex. In this paper, Morris-Lecar neuron neuron is utilized to implement bio-inspired memristive spiking neural network for unsupervised learning applications. The spike timing dependent plasticity learning mechanism has been applied as the learning scheme in the system. The memristive implementation of the Morris-Lecar neuron has been analyzed. Also the memristors are utilized as the synapses for the proposed system to reproduce long term potentiation and long term depression. The proposed platform is tested for pattern classification applications and the results are successfully confirmed its functionality.

Logic Design on Mirrored Memristive Crossbars

This brief presents a hybrid CMOS-memristor logic design and implementation method on a novel mirrored crossbar architecture. The proposed structure supports in-memory computation and needs only one computational step to perform basic Boolean expressions. This logic can provide multiple fanins and/or fanouts, and does not have a destructive effect on input devices’ logical states. Various logic gates have been designed using the proposed structure. Simulation results and practical design constraints for different logic functions are presented, which confirms functionality of the method and its capability for large-scale memristive computations.

A hybrid memristor-CMOS multiplier design based on memristive universal logic gates

Memristor is considered as one of the promising solutions to the fundamental limitations of the VLSI systems. Logic implementation with memristor device by considering its compatibility with CMOS fabric provides a new vision for digital logic circuits. This work presents a 2 by 2 multiplier cell design using a hybrid CMOS-memristor universal gate. The universal gate based implementation approach is the extension for memristor ratioed logic (MRL) with lower implementation cost. Simulation results confirm functionality of the proposed circuit. This circuit requires 16 memristors, 8 transistors and only one computational time step for multiplication. Compared with previous works, this approach presents considerably lower implementation cost.

A novel CVNS adder with memristive analog memory

The Continuous Valued Number System (CVNS) is a new approach in computer arithmetic to develop high performance and efficient arithmetic units. In this paper, CVNS-based computation scheme is applied to design a memristive analog adder and it has been demonstrated that this technique is a viable alternative approach to implement multidigit arithmetic system with multilevel memory devices. The proposed CVNS adder has addition and modulo configurations to perform CVNS addition. A mapping circuit has been designed for modulo operation. The proposed memristive CVNS-based adder has been simulated and analyzed for different CVNS values with radix-10 and 2-digit analog environment resolution. The simulations are shown acceptable accuracy and the presented system performance promises an analog memristive computation method for future in-memory computation systems.

Accurate charge transport model for nanoionic memristive devices

Abstract Memristors have the potential to significantly impact the memory market, and have demonstrated the potential for analog computing within a sub-class of neuro-inspired information processing. In order to enable circuit designers to use and test memristor/CMOS hybrid circuits, it is necessary to have an accurate and reliable memristor model. In this work, a new memristor model based on Charge Transport Mechanism (CTM) is presented. This paper analyzes different current mechanisms that exist in Schottky barrier region of memristors: direct tunneling, thermionic emission, and Ohmic currents. The proposed memristor model is based on direct tunneling and Ohmic conduction, and it accounts for physical phenomena within memristive devices. The presented model shows a relative root mean square error of about 0.25 when compared with experimental results for a Ag/TiO2/ITO memristor. It also shows better accuracy in comparison with other modeling approaches published in the literature. The proposed model is implemented in SPICE and a subcircuit for the model is provided.

Hyperbolic tangent passive resistive-type neuron

In this paper, design of a passive resistive-type neuron is proposed to generate the hyperbolic tangent function as the activation function. The proposed resistive-type neuron has the advantage of not needing any biasing voltage and therefore its power consumption is low. The neuron circuit is designed and simulated in 180 nm CMOS technology. The proposed neuron shows a good approximation with maximum error and average error from the ideal hyperbolic tangent function by 19.7% and 6.88% respectively. The power consumption of the proposed neuron is 62.5 μW while the standby power is zero. Also the proposed neuron is applied in a large neural network and the results shows good functionality. The pattern recognition neural network implemented using the proposed neuron is consumed 295 μW power that is approximately 59.86% less than the same network proposed with the previous analog hyperbolic tangent designed neuron.