Arash Ahmadi

Biologically Inspired Spiking Neurons: Piecewise Linear Models and Digital Implementation

There has been a strong push recently to examine biological scale simulations of neuromorphic algorithms to achieve stronger inference capabilities. This paper presents a set of piecewise linear spiking neuron models, which can reproduce different behaviors, similar to the biological neuron, both for a single neuron as well as a network of neurons. The proposed models are investigated, in terms of digital implementation feasibility and costs, targeting large scale hardware implementation. Hardware synthesis and physical implementations on FPGA show that the proposed models can produce precise neural behaviors with higher performance and considerably lower implementation costs compared with the original model. Accordingly, a compact structure of the models which can be trained with supervised and unsupervised learning algorithms has been developed. Using this structure and based on a spike rate coding, a character recognition case study has been implemented and tested.

Digital Multiplierless Implementation of Biological Adaptive-Exponential Neuron Model

High-accuracy implementation of biological neural networks is a computationally expensive task, specially, for large-scale simulations of neuromorphic algorithms. This paper proposes a set of models for biological spiking neurons, which are efficiently implementable on digital platforms. Proposed models can reproduce different biological behaviors with a high precision. The proposed models are investigated, in terms of digital implementation feasibility and costs, targeting low-cost hardware implementation. Hardware synthesis and physical implementations on a field-programmable gate array show that the proposed models can produce biological behavior of different types of neurons with higher performance and considerably lower implementation costs compared with the original model.

Optimized implementation of memristor-based full adder by material implication logic

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.

Digital Implementation of a Biological Astrocyte Model and Its Application

This paper presents a modified astrocyte model that allows a convenient digital implementation. This model is aimed at reproducing relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system. Accordingly, we investigate the feasibility of a digital implementation for a single astrocyte and a biological neuronal network model constructed by connecting two limit-cycle Hopf oscillators to an implementation of the proposed astrocyte model using oscillator-astrocyte interactions with weak coupling. Hardware synthesis, physical implementation on field-programmable gate array, and theoretical analysis confirm that the proposed astrocyte model, with considerably low hardware overhead, can mimic biological astrocyte model behaviors, resulting in desynchronization of the two coupled limit-cycle oscillators.

Memristor-based linear feedback shift register based on material implication logic

Memristor as an emerging history dependent nanometer scaled element will play an important role in future nanoelectronic computing technologies. Some pure and hybrid memristor-based implementation techniques have been proposed in recent years. Material implication logic is one of the significant areas for memristor-based logic implementation. In this paper a memristor-based linear feedback shift register is implemented based on material implication logic. It is implemented by 8 memristors which is considerably used less area in comparison with conventional CMOS-based peers. Also the proposed memristor-based LFSR circuit needs 55 computational steps for generating a 4-bits number.

Symbolic noise analysis approach to computational hardware optimization

This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.

Word-Length Oriented Multiobjective Optimization of Area and Power Consumption in DSP Algorithm Implementation

The word-length of functional units (FU) has a great impact on design costs. This paper addresses the problem of choosing different word-lengths for each FU while considering circuit area and power consumption. A high-level synthesis tool is used to minimize the circuit area and power consumption by selecting an optimal word-length for each FU in the system. Our results demonstrate that by customizing word lengths to non-standard sizes, savings can be made in the overall area and power without losing accuracy

Digital multiplierless implementation of the biological FitzHugh-Nagumo model

High-accuracy implementation of biological neural networks (NN) is a task with high computational overheads, especially in the case of large-scale realizations of neuromorphic algorithms. This paper presents a set of piecewise linear FitzHugh-Nagumo (FHN) models, which can reproduce different behaviors, similar to the biological neuron. This paper presents a set of equations as a model to describe the mechanisms of a single neuron, which are implementable on digital platforms. Simulation results show that the model can reproduce different behaviors of the neuron. The proposed models are investigated, in terms of digital implementation feasibility and computational overhead, targeting low-cost hardware realization. Hardware synthesis and physical implementations on FPGA show that the proposed models can produce a range of neuron behaviors with higher performance and lower implementation costs compared to the original model.

Realistic Hodgkin–Huxley Axons Using Stochastic Behavior of Memristors

Ion-channel variability has critical effect on the spike initiation and propagation in nervous system. Noise can play a constructive role leading to increased reliability or regularity of neuronal firing and spike propagation in the nervous system. In this paper we show that memristors can be considered as an electronic analogous of the Hodgkin–Huxley ion channels not only in terms of threshold switching effect but also in terms of stochastic behavior. In other words, memristor can also implement stochastic version of Hodgkin–Huxley equation. Switching effect in memristive devices is thermodynamically driven, which is stochastic in nature. We show that if the intrinsic stochastic behavior of memristor is taken into account, memristor based neuristor can also implement stochastic version of Hodgkin–Huxley axon model in generation of action potential. Ion channel variability in neurons can be modeled by intrinsic stochastic behavior of memristor. We incorporate noise in the memristor model by adding white Gaussian noise to the deterministic part of dynamical state evolution function of the memristor. We study the reliability of spike timing for spike train generated by memristor based neuristor in which the noise included memristor model is used. Also, the reliability of spike propagation along thin axons is discussed. A series connection of neuristors can be used as an axon in which neuristor acts as a node of Ranvier on an axon. Probabilistic nature of spike propagation on thin axons can be modeled using neuristor in which the variability nature of memristor is included.

Multiple-Width Bus Partitioning Approach to Datapath Synthesis

A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of functional units has a great impact on design costs. A combination of both methods is used in this paper in the form of a partitioned shared bus structure, in which every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the FUs as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a multi-objective optimization genetic algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting an optimal grouping and word-length for each FU in a shared bus system. Results demonstrate that savings can be made in the overall system costs by applying this method.