Amirali Shayan

Dynamically heterogeneous cores through 3D resource pooling

This paper describes an architecture for a dynamically heterogeneous processor architecture leveraging 3D stacking technology. Unlike prior work in the 2D plane, the extra dimension makes it possible to share resources at a fine granularity between vertically stacked cores. As a result, each core can grow or shrink resources, as needed by the code running on the core. This architecture, therefore, enables runtime customization of cores at a fine granularity and enables efficient execution at both high and low levels of thread parallelism. This architecture achieves performance gains from 9-41%, depending on the number of executing threads, and gains significant advantage in energy efficiency of up to 43%.

Reducing peak power with a table-driven adaptive processor core

The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most directly impacts the processor design, packaging, and power delivery. This research proposes a new architecture which provides a significant decrease in peak power with limited performance loss. It does this through the use of a highly adaptive processor. Many components of the processor can be configured at different levels, but because they are centrally controlled, the architecture can guarantee that they are never all configured maximally at the same time. This paper describes this adaptive processor and explores mechanisms for transitioning between allowed configurations to maximize performance within a peak power constraint. Such an architecture can cut peak power by 25% with less than 5% performance loss; among other advantages, this frees 5.3% of total core area used for decoupling capacitors.

3D stacked power distribution considering substrate coupling

Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional System on Chip (SoC). In this paper a comprehensive modeling of the TSV and stacked power grid with frequency dependent parasitic is proposed. The analytical model considers the impact of the substrate coupling between the TSVs and layers grid. A frequency domain based analysis flow is introduced to incorporate frequency dependent parasitics. The design of a reliable power distribution network is formulated as an optimization problem to minimize power noise under reliability and electro-migration constraints. Experimental results demonstrate the efficacy of the problem formulation and solution technique.

Worst-case noise prediction with non-zero current transition times for early power distribution system verification

A novel method of predicting the worst-case noise of a power distribution system is proposed in this paper. This method takes into account the effect of the transition time of load currents, and thus allows a more realistic worst-case noise prediction. A dynamic programming algorithm is introduced on the time-domain impulse response of the power distribution system, and a modified Knuth-Yao Quadrangle Inequality Speedup is developed which reduces the time complexity of the algorithm to O(nmlog n), where n is the number of discretized current values and m is the number of zeros of the system impulse response. With the algorithm, the worst-case noise behavior of the power distribution system is investigated with respect to the transition time. Experimental results show that assuming a zero current transition time leads to an overly pessimistic worst-case noise prediction.

3D power distribution network co-design for nanoscale stacked silicon ICs

In this paper, we propose an efficient flow for the analysis and co-design of large 3D power distribution networks (3D PDN). In this flow, the network is modeled in frequency domain and thus can take advantage of parallel computing. The proposed flow significantly reduces the CPU time while obtaining accurate results as compared to commercial simulation tools. In the established 3D PDN model, we incorporate the on-chip voltage regulator module (VRM) and effect of on-chip inductance. The impact of each design parameter of the 3D PDN on simultaneous switching noise (SSN) is investigated based on the model.

Analyzing High-Density ECG Signals Using ICA

The analysis of ECG signals is of fundamental importance for cardiac diagnosis. Conventional ECG recordings, however, use a limited number of channels (12) and each records a mixture of activities generated in different parts of the heart. Therefore, direct observation of the ECG signals collected on the body surface is likely an inefficient way to study and diagnose cardiac abnormalities. This study describes new experimental and analytical methods to capture more meaningful ECG component signals, each representing more directly a physical cardiac source. This study first describes a simply applied method for collecting high-density ECG signals. The recorded signals are then separated by independent component analysis (ICA) to obtain spatially fixed and temporally independent component activations. Results from five subjects show that P-, QRS-, and T-waves can be clearly separated from the recordings, suggesting ICA might be an effective and useful tool for high-density ECG analysis, interpretation, and diagnosis.

An adaptive parallel flow for power distribution network simulation using discrete Fourier transform

A frequency-time-domain co-simulation flow using discrete Fourier transform (DFT) is introduced in this paper to analyze large power distribution networks (PDNs). The flow not only allows designers to gain an insight to the frequency-domain characteristics of the PDN but also to obtain accurate time-domain voltage responses according to different load current profiles. An adaptive method achieves accurate results within even shorter time compared to the basic DFT flow. In addition, parallel processing is incorporated which leads to a significant reduction in simulation time. Error bounds of the DFT flow are derived to assure the accuracy of simulation results. Experimental results show that the proposed flow has a relative error of 0.093% and a speedup of 10× compared to SPICE transient simulation with a single processor.

On the bound of time-domain power supply noise based on frequency-domain target impedance

One of the popular design methodologies for power distribution networks (PDNs) is to identify a target impedance to be met across a broad frequency range. The methodology is based on the assumption that the ratio of the time-domain maximum output voltage noise to the multiplication of target impedance and time-domain maximum input current is no more than one. In this paper, the ratios for different impedance profiles are analyzed, and the assumption is proved to be not necessarily true. Particularly, for second-order impedances, the maximum ratio can be two. Several cases with real PDN structures are investigated to support our analysis. A real case of the complete PDN path with the ratio of 1.585 is given.

On-chip power network optimization with decoupling capacitors and controlled-ESRs

In this paper, we propose an efficient approach to minimize the noise on power networks via the allocation of decoupling capacitors (decap) and controlled equivalent series resistors (ESR). The controlled-ESR is introduced to reduce the on-chip power voltage fluctuation, including both voltage drop and overshoot. We formulate an optimization problem of noise minimization with the constraint of decap budget. A revised sensitivity calculation method is derived to consider both voltage drop and overshoot. The sequential quadratic programming (SQP) algorithm is adopted to solve the optimization problem where the revised sensitivity is regarded as the gradient. Experimental results show that considering voltage drop without overshoot leads to underestimating noise by 4.8%. We also demonstrate that the controlled-ESR is able to reduce the noise by 25% with the same decap budget.

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network

In this paper, an efficient parallel flow for the design of the full power distribution network (PDN) is proposed. The analysis demonstrates the impact of the voltage regulator model in both frequency and time domain response. Based on the experimental results, it is observed that including the voltage regulator model in the PDN model increases the transient voltage drop and PDN response which need to be considered for nanoscale ICs. The flow is optimized using parallel processing to speedup slow response simulation time of the off chip voltage regulator. The study highlights the power integrity issues related to voltage regulator in broadband frequency ranges. The experimental results show speedup of up to 22 times with single processor and more than 430 times using up to 200 processors compared to HSPICE and other commercial simulators. The PDN simulation time is reduced from hours to less than a minute.