Wanping Zhang

3D stacked power distribution considering substrate coupling

Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional System on Chip (SoC). In this paper a comprehensive modeling of the TSV and stacked power grid with frequency dependent parasitic is proposed. The analytical model considers the impact of the substrate coupling between the TSVs and layers grid. A frequency domain based analysis flow is introduced to incorporate frequency dependent parasitics. The design of a reliable power distribution network is formulated as an optimization problem to minimize power noise under reliability and electro-migration constraints. Experimental results demonstrate the efficacy of the problem formulation and solution technique.

3D power distribution network co-design for nanoscale stacked silicon ICs

In this paper, we propose an efficient flow for the analysis and co-design of large 3D power distribution networks (3D PDN). In this flow, the network is modeled in frequency domain and thus can take advantage of parallel computing. The proposed flow significantly reduces the CPU time while obtaining accurate results as compared to commercial simulation tools. In the established 3D PDN model, we incorporate the on-chip voltage regulator module (VRM) and effect of on-chip inductance. The impact of each design parameter of the 3D PDN on simultaneous switching noise (SSN) is investigated based on the model.

Analyzing High-Density ECG Signals Using ICA

The analysis of ECG signals is of fundamental importance for cardiac diagnosis. Conventional ECG recordings, however, use a limited number of channels (12) and each records a mixture of activities generated in different parts of the heart. Therefore, direct observation of the ECG signals collected on the body surface is likely an inefficient way to study and diagnose cardiac abnormalities. This study describes new experimental and analytical methods to capture more meaningful ECG component signals, each representing more directly a physical cardiac source. This study first describes a simply applied method for collecting high-density ECG signals. The recorded signals are then separated by independent component analysis (ICA) to obtain spatially fixed and temporally independent component activations. Results from five subjects show that P-, QRS-, and T-waves can be clearly separated from the recordings, suggesting ICA might be an effective and useful tool for high-density ECG analysis, interpretation, and diagnosis.

Efficient Power Network Analysis Considering Multidomain Clock Gating

In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily converted to a time-domain waveform. Then, an algorithm is proposed to find the worst-case voltage variation and corresponding clock gating patterns, through superimposing the voltage responses caused by all domains working separately. The major computation of the whole framework is solving the frequency-domain equation system, whose complexity is about O(NalphaD log f max), where alpha is between one and two if using an iterative solver from the PETSc library. N is the node number, f max is the upper bound of frequency, and D is the number of clock domains. Numerical results show that the proposed simulation method is up to several hundred times faster than commercial fast simulators, like HSPICE and MSPICE. In addition, the proposed method is able to analyze large-scale power networks that the commercial tools are not able to afford.

Fast power network analysis with multiple clock domains

This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transform on the input current sources to derive the analytical formula. Then, we calculate the circuit frequency response with logarithmic scale frequency components. The frequency domain response is approximated by a rational function using vector fitting modeling. The rational function is used to derive the natural frequency of the power ground networks, and can be converted back into time domain easily. Based on the analysis results, we then present the worst case clock gating pattern algorithm to analyze the power networks with multiple clock domains. The most expensive part of the proposed algorithm is the matrix solving: O(F(N) ldr log f ldr D). Function F is the complexity of iterative solution of complex matrix with dimension N. We assume that there are D clock domains and the frequency spans from 0 to f Hz. Experimental results show that our method is up to 60X faster than HSPICE, and can analyze large circuits which are not affordable by HSPICE.

On-chip power network optimization with decoupling capacitors and controlled-ESRs

In this paper, we propose an efficient approach to minimize the noise on power networks via the allocation of decoupling capacitors (decap) and controlled equivalent series resistors (ESR). The controlled-ESR is introduced to reduce the on-chip power voltage fluctuation, including both voltage drop and overshoot. We formulate an optimization problem of noise minimization with the constraint of decap budget. A revised sensitivity calculation method is derived to consider both voltage drop and overshoot. The sequential quadratic programming (SQP) algorithm is adopted to solve the optimization problem where the revised sensitivity is regarded as the gradient. Experimental results show that considering voltage drop without overshoot leads to underestimating noise by 4.8%. We also demonstrate that the controlled-ESR is able to reduce the noise by 25% with the same decap budget.

Clock Skew Analysis via Vector Fitting in Frequency Domain

An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and derive the rational approximate with the help of vector fitting [9]. There are two aspects that contribute to the time efficiency of the method. One is CSAV solves the state equation only on selected frequency points, which significantly reduce the amount of time for equation solving. The other is CSAV performs vector fitting and waveform recovery only on user specified nodes, which save the unnecessary computation on the nodes which are not concerned by user. The complexity of our method is O( lceillg fmaxrceilNalpha + lceillg fmaxrceil 2NaNout), where fmax is proportional to the knee frequencyquency of input signal, N is the node number of the circuit, a is a constant around 1.3, Na is the order of approximation and Nout is the number of output nodes. Our experimental results show that compared with Hspice, CSAV achieves speed-up up to 35 times while the error is only 1%. Moreover, computational saving of CSAV grows with circuit size, which makes this method especially promising for large cases.

Finding the worst voltage violation in multi-domain clock gated power network

This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (ILP) formulation is proposed to identify the worst-case gating pattern and the maximum variation area. The ILP based method is significantly faster than a conventional method based on enumeration. The experimental results are also compared with a case where peak voltage variation is induced, which shows the latter technique largely underestimated the overall variation effect.

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network

In this paper, an efficient parallel flow for the design of the full power distribution network (PDN) is proposed. The analysis demonstrates the impact of the voltage regulator model in both frequency and time domain response. Based on the experimental results, it is observed that including the voltage regulator model in the PDN model increases the transient voltage drop and PDN response which need to be considered for nanoscale ICs. The flow is optimized using parallel processing to speedup slow response simulation time of the off chip voltage regulator. The study highlights the power integrity issues related to voltage regulator in broadband frequency ranges. The experimental results show speedup of up to 22 times with single processor and more than 430 times using up to 200 processors compared to HSPICE and other commercial simulators. The PDN simulation time is reduced from hours to less than a minute.

Noise minimization during power-up stage for a multi-domain power network

With the popularity of Multiple Power Domain (MPD) design, the multi-domain power network noise analysis and minimization is becoming important. This paper describes an efficient heuristic algorithm to arrange the power-up sequence in a multi-domain power network in order to minimize the noise. We present a formulation of this problem and show it is NP-complete. Therefore, we propose a simulated annealing (SA) based algorithm with preprocessing. Experimental results show that the proposed algorithm can minimize the noise close to the minimal values. In terms of efficiency, the SA algorithm is more than hundreds of times faster than the enumerating method and the running time scales well for these cases with the number of domains. In addition, we discuss the trade off between power-up efficiency and noise.