Amirhossein Alimohammad

A Compact and Accurate Gaussian Variate Generator

A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to plusmn15 times the standard deviation sigma) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of plusmn6.66sigma. To accurately achieve a range of plusmn9.4sigma, the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests.

Compact Rayleigh and Rician fading simulator based on random walk processes

This article describes a significantly improved sum-of-sinusoids-based model for the accurate simulation of time-correlated Rayleigh and Rician fading channels. The proposed model utilises random walk processes instead of random variables for some of the sinusoid parameters to more accurately reproduce the behaviour of wireless radio propagation. Every fading block generated using our model has accurate statistical properties on its own and hence, unlike previously proposed models, there is no need for time-consuming ensemble-averaging over multiple blocks. Using numerical simulation it is shown that the important statistical properties of the generated fading samples have excellent agreement with the theoretical reference functions. A fixed-point hardware implementation of the corresponding Rayleigh and Rician fading channel simulator on a field-programmable gate array (FPGA) is presented. By efficiently scheduling the operations, the reconfigurable fading channel simulator is compact enough that it can be efficiently used to simulate multipath scenarios and multiple-antenna systems (e.g. a 4×4 MIMO channel) using a single FPGA.

A Single FPGA Filter-Based Multipath Fading Emulator

Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporally-correlated fading variates for emulating multipath fading radio channels. The implemented fading emulator is flexible enough to model different propagation scenarios accurately and is compact enough that it can be implemented on the same FPGA with the design under test (DUT) for greater emulation efficiency and speed-up. Several streams of Rayleigh or Rician fading variates are generated by passing independent samples of Gaussian noise through spectrum shaping filters. The new baseband emulator is fully parameterizable and can emulate a wide variety of single and multiple antenna scenarios.

Modeling and Hardware Implementation Aspects of Fading Channel Simulators

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. Two major approaches have been widely used to produce statistically accurate fading variates, namely shaping the flat spectrum of Gaussian variates using digital filters and sum-of-sinusoids (SOS)-based methods. Efficient design and implementation techniques for these schemes are of particular importance in the design and verification of wireless systems with a relatively large number of channels, such as ad hoc networks. This paper considers the modeling and implementation aspects of fading channel simulators. First, we present a novel computationally efficient implementation of a filter-based fading channel simulator on a single field-programmable gate array (FPGA) device. The new technique significantly alleviates the challenges of real-world testing of communication systems by introducing a fast and area-efficient FPGA implementation of the fading channel. Our fixed-point implementation of a Rayleigh-fading channel simulator on an FPGA utilizes only 3% of the configurable slices, 10% of the dedicated multipliers, and 1% of the available memories on a Xilinx Virtex-II Pro XC2VP100-6 FPGA, while the simulator operates 12.5 times faster than the example sample rate. Then, we describe a compact implementation of the SOS-based fading simulator that uses only 1% of the configurable slices and 1% of the available memories on the same FPGA device while generating over 200 million complex Rayleigh-fading variates per second.

A Compact Single-FPGA Fading-Channel Simulator

This brief presents a novel computationally efficient design and implementation of a Rayleigh flat fading-channel simulator. To generate complex Gaussian variates with the required U-shaped power spectrum, the simulator utilizes an infinite-impulse response (IIR) spectrum shaping filter followed by multistage interpolators and low-pass IIR filters. The new simulator significantly simplifies the characterization of wireless systems by providing a fast and area-efficient field-programmable gate array (FPGA) implementation of the fading channel. Our fixed-point Rayleigh fading-channel simulator utilizes only 4% of the configurable slices, 20% of the dedicated multipliers, and 2% of the available memories on a Xilinx Virtex2P XC2VP100-6 FPGA, while generating 25 million fading variates per second. The parameterized fading-channel simulator can be readily reconfigured to accurately simulate a wide variety of different channel characteristics.

A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels

We present a fading model with a compact and fast hardware implementation suitable for correlated Rayleigh fading channel simulators. The proposed scheme is based on the sum-of-sinusoids model because of its flexibility and efficient mapping onto hardware. Using numerical simulation, it is shown that the statistical properties of the generated fading variates match the theoretical reference model. Since the cross-correlations between sequences of generated fading variates are small, this model can also be used to implement a time-correlated multiple-input multiple-output (MIMO) fading channel simulator on a single field-programmable gate array (FPGA). The MIMO channel simulator can also be extended to support spatial correlation between generated fading samples. An implementation of a spatiotemporally correlated (4, 4) MIMO channel simulator on a Xilinx Virtex-II Pro XC2VP100-6 FPGA uses 46% of the configurable slices, 30% of the dedicated multipliers, and 32% of the on-chip block memories while generating 4 times 201 million 2 times 16-bit complex-valued fading samples per second.

An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading

We present an ultracompact and fast hardware simulator for Rayleigh and Rician fading channels. To ensure numerical robustness and an efficient mapping onto hardware, the fading simulator uses the sum-of-sinusoids technique with N = 32 sinusoids added up to model each fading path. Fading samples are generated at a low rate and then are passed to an interpolator, which computes the final samples at the desired baseband rate. We propose a new time-multiplexed datapath that uses a differential approach. Instead of directly generating the fading samples, the datapath generates the discrete difference between fading samples. The proposed simulator is so compact that an entire 4 × 4 multiple-input-multiple-output (MIMO) fading channel can be implemented on a small fraction of a single field-programmable gate array (FPGA). On a Xilinx Virtex-4 XC4VLX200-11 FPGA, up to 1184 different paths can be simultaneously implemented while generating 1184 × 342 million 2 × 16-bit complex-valued fading samples per second.

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.

An Accurate and Compact Rayleigh and Rician Fading Channel Simulator

A stochastic sum-of-sinusoids based simulation model is proposed for Rayleigh and Rician fading channels. The time-averaged statistical properties of the new model have been significantly improved compared to existing models. Verification of the proposed fading simulator is carried out by comparing its measured statistical properties with the properties of the ideal reference models. The simulator utilizes a time-overlapped implementation strategy to provide a compact design suitable for multiple antenna simulators. An implementation of the resulting Rician fading simulator on a Xilinx Virtex-II Pro XC2VP100- 6 FPGA uses only 2% of the configurable slices, 1% of the dedicated multipliers, and 2% of the on-chip block memories while generating 201 million 2 times 16-bit complex-valued fading samples per second. The scalable design of the fading channel simulator enables a straightforward implementation of multiple antenna channels and different diversity schemes.

An Improved SOS-Based Fading Channel Emulator

We describe an improved scheme for simulating Rayleigh fading channels which accurately reproduces the required channel statistics. The new scheme is based on the sum- of-sinusoids Rayleigh fading model because of its flexibility and efficient mapping onto hardware. Using numerical simulation it is shown that the statistical properties of the generated fading variates, such as the probability density function, the autocorrelation, and the level crossing rate, follow the desired theoretical properties. A fixed-point implementation of the fading channel simulator on a field-programmable gate array utilizes only 5% of the configurable slices and generates over 200 million 16-bit fading variates per second.