Bruce F. Cockburn

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.

A Compact and Accurate Gaussian Variate Generator

A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to plusmn15 times the standard deviation sigma) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of plusmn6.66sigma. To accurately achieve a range of plusmn9.4sigma, the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests.

Tutorial on semiconductor memory testing

This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.

A scalable LDPC decoder ASIC architecture with bit-serial message exchange

We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architectures potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250Mbps, a core area of 6.96mm^2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.

Compact Rayleigh and Rician fading simulator based on random walk processes

This article describes a significantly improved sum-of-sinusoids-based model for the accurate simulation of time-correlated Rayleigh and Rician fading channels. The proposed model utilises random walk processes instead of random variables for some of the sinusoid parameters to more accurately reproduce the behaviour of wireless radio propagation. Every fading block generated using our model has accurate statistical properties on its own and hence, unlike previously proposed models, there is no need for time-consuming ensemble-averaging over multiple blocks. Using numerical simulation it is shown that the important statistical properties of the generated fading samples have excellent agreement with the theoretical reference functions. A fixed-point hardware implementation of the corresponding Rayleigh and Rician fading channel simulator on a field-programmable gate array (FPGA) is presented. By efficiently scheduling the operations, the reconfigurable fading channel simulator is compact enough that it can be efficiently used to simulate multipath scenarios and multiple-antenna systems (e.g. a 4×4 MIMO channel) using a single FPGA.

Deterministic tests for detecting single V -coupling faults in RAMs

We consider the problem of detecting singleV-coupling faults (as defined by Nair, Thatte, and Abraham) inn×1 random-access memories (RAMs). First we derive a lower bound of 2V−2nlog2n+(2V+3)n on the length of any test that detects all singleV-coupling faults, for 2≤V≤47 andn=2e whereeɛ{8,...,34}. In the derivation we make use of a family of binary codes which we call (n, θ)-exhaustive codes. We then describe a procedure which, given any (n, V−1)-exhaustive code, constructs a test that detects all singleV-coupling faults, forn≥V>2. Following this approach, optimal (n,1)- and (n, 2)-exhaustive codes are used to construct S2CTEST and S3CTEST, which are efficient tests of length 10n and 4nlog2n+18n that detect all single 2- and 3-coupling faults, respectively. S3CTEST is roughly five times shorter, for current RAM capacities, than Papachristou and Sahgals test of length 24n[log2n]+n. Codes generated according to Tang and Chen are used similarly to construct S4CTEST and S5CTEST, which are tests of approximate length 8.6n(log2n)1.585 and 9.6n(log2n)2.322 that detect all single 4- and 5-coupling faults, respectively. S5CTEST has the interesting property of being able to detect all single physical neighborhood pattern-sensitive faults without requiring the mapping from logical cell addresses to physical cell locations. S5CTEST also detects the scrambled pattern-sensitive fault recently proposed by Franklin and Saluja; moreover, the new test is approximately fourteen times shorter (for 1 and 4 Mbit RAMs) than the test they describe.

A Single FPGA Filter-Based Multipath Fading Emulator

Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporally-correlated fading variates for emulating multipath fading radio channels. The implemented fading emulator is flexible enough to model different propagation scenarios accurately and is compact enough that it can be implemented on the same FPGA with the design under test (DUT) for greater emulation efficiency and speed-up. Several streams of Rayleigh or Rician fading variates are generated by passing independent samples of Gaussian noise through spectrum shaping filters. The new baseband emulator is fully parameterizable and can emulate a wide variety of single and multiple antenna scenarios.

Modeling and Hardware Implementation Aspects of Fading Channel Simulators

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. Two major approaches have been widely used to produce statistically accurate fading variates, namely shaping the flat spectrum of Gaussian variates using digital filters and sum-of-sinusoids (SOS)-based methods. Efficient design and implementation techniques for these schemes are of particular importance in the design and verification of wireless systems with a relatively large number of channels, such as ad hoc networks. This paper considers the modeling and implementation aspects of fading channel simulators. First, we present a novel computationally efficient implementation of a filter-based fading channel simulator on a single field-programmable gate array (FPGA) device. The new technique significantly alleviates the challenges of real-world testing of communication systems by introducing a fast and area-efficient FPGA implementation of the fading channel. Our fixed-point implementation of a Rayleigh-fading channel simulator on an FPGA utilizes only 3% of the configurable slices, 10% of the dedicated multipliers, and 1% of the available memories on a Xilinx Virtex-II Pro XC2VP100-6 FPGA, while the simulator operates 12.5 times faster than the example sample rate. Then, we describe a compact implementation of the SOS-based fading simulator that uses only 1% of the configurable slices and 1% of the available memories on the same FPGA device while generating over 200 million complex Rayleigh-fading variates per second.

An investigation into crosstalk noise in DRAM structures

The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. In this article we describe the results of a simulation study into the effects of crosstalk among DRAM wordlines and bitlines for present and future technology nodes predicted by the roadmap. An analog simulator was used to solve the associated transmission line equations derived from Maxwells equations in the time domain. Hence, we not only considered interconnect resistances and capacitances, but also inductances and realistic wave propagation effects. The circuit parameters of the simulation models were extracted from standard DRAM geometries implied by the roadmap data. Various bitline-bitline and wordline-wordline coupling scenarios were then studied in simulation. Our results suggest that down until the 22-nm node, single bitline twisting will continue to be effective against bitline-bitline coupling, but that wordline-wordline coupling effects will become more problematic.

Detection of coupling faults in RAMs

This article presents results fundamental to the problem of detecting coupling faults in random access memories (RAMs). Good and faulty memories are represented as Mealy automata using the formal framework for sequential machine testing developed by Brzozowski and Jürgensen. A precise description of the coupling fault is used to define two fault models: “general coupling,” which is the set of all possible multiple coupling faults, and “general toggling,” which is a subset of general coupling. A lower bound of 2n2 + n is derived on the length of any test that detects general toggling in an n cell memory; a test by Marinescu is thereby shown to be optimal for this fault model. A lower bound of 2n2 + 3n is derived on the length of any test that detects general coupling, and a corresponding test of length 2n2 + 4n is described. Abadir and Reghbatis improved version of the traditional test GALPAT, of length 4n2 + 4n, is shown to detect general toggling but not general coupling.