Amit Krishna Dwivedi

Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.

Nonvolatile and Robust Design of Content Addressable Memory Cell Using Magnetic Tunnel Junction at Nanoscale Regime

This paper proposes an efficient and robust design of content addressable memory (CAM) system. Design metrics, such as search time, power dissipation, power-delay product (PDP), and energy-delay product (EDP), of the proposed design are compared with those of previously reported CAM cell found in the literature. CAM cell presented in this paper offers 2.589× improvement in search time, 2.725× improvement in PDP, and 2.729× improvement in EDP for mismatch 1 at 700 mV. It exhibits 2.257× improvement in search time, 2.38× improvement in PDP, and 2.389× improvement in EDP for mismatch 0 at 700 mV. The proposed CAM cell also proves its efficiency in terms of power consumption, which is one of the most concerned design issues. It offers 1.0526× improvement in power consumption for mismatch 1 and 1.054× improvement in power consumption for mismatch 0. The proposed CAM cell is also analyzed to investigate the impact of tunneling magnetoresistance variations on power consumption, PDP, EDP, search time, and search-time variability. In addition, this paper also proposes an efficient match line sensing scheme for the proposed CAM cell.

Design of magnetic tunnel junction-based tunable spin torque oscillator at nanoscale regime

This study proposes a spintronic based compact tunable nano-sized RF oscillator. The proposed design provides parametric performance improvement as compared with the designs already reported in literature. This design also offers higher operating frequency up to range of several GHz, which can be tuned by a DC bias current. The proposed magnetic tunnel junction-spin torque oscillators (MTJ-STO) model overcomes the limitation of low output power which is prime issue in spin torque oscillators (STOs). This is achieved by employing multi-stage amplifier with impedance matching stages. In addition to that, mutual phase locking mechanism of STOs is introduced to act as a remedy for broadening of the spectrum linewidth, which is a critical issue in traditional oscillators. The hybrid model presented in this study contains spin torque based MTJ, which is compatible with CMOS technology. The modelling of proposed circuit has been done in Verilog-A and simulation results have been verified using HSPICE.

A Compact Low Power High Frequency Pulse Generator

This paper proposes a compact, low power high frequency trigger pulse generator circuit. Delay-introducing circuit that can incorporate a certain amount of delay during signal processing while maintaining the signal integrity is utilized in the proposed design. This paper evaluates performance of various delay-introducing circuits in terms of different design matrices. Further, this paper exploits the low power consuming delay element to implement the proposed trigger pulse generator. The proposed design generates very high frequency pulses at the cost of negligible power consumption. The effectiveness of the proposed circuit is presented by producing ultra-thin pulses of pulse duration 92.35 ps while consuming power of only 1.502 μW. Extensive simulations are carried out on SPICE @ 16-nm predictive technology model to verify the proposed design.

Threshold voltage extraction and its reliance on device parameters @ 16-nm process technology

Threshold voltage (VTH) is a prime device parameter to model on-off transition characteristics for MOSFETs. Accurate VTH of the device is evaluated by several estimation techniques reported in literature. However, these estimated values of VTH differ from the exact values due to various short channel effects (SCEs) and non-idealities present in the devices. VTH depends on various process parameters, device dimensions and also on the methodology used for extracting. With the technology scaling various effects come into picture while extracting VTH. This paper presents a comparative study of various threshold estimation techniques @ 16-nm technology node. Further, dependence of VTH on various design metrics and process parameter is also presented for different technology nodes. This work analyzes the effect of reduced process technology parameters on VTH. Results are verified by extensive simulation on SPICE.

Performance Enhancement of Full Adder Circuit: Current Mode Operated Majority Function Based Design

Paper reports a novel majority function based current mode operated compact sized robust design of 1-bit full adder (FA) circuit. The focus of this work is to reduce the power supply consumption required for performing arithmetic operations by introducing a novel and efficient way of computing 1-bit addition relying on current mode operation. Presented high speed FA design utilizes only 7Ts, per bit, to implement sum and carry functions. The majority function based proposed FA circuit requires lesser number of transistors as compared to the conventional 28Ts FA circuit. A current mirror (CM) circuit has been incorporated in the proposed design to act as a constant current reference to drive the whole circuitry. Further, to evince the uniqueness of the proposed FA design, comparisons have been drawn with various other standard FA designs in terms of different design metrics such as power consumption, supply voltage requirement, power delay product (PDP), energy delay product (EDP) and operating speed. Extensive simulations have been performed using Virtuoso Analog Design Environment of Cadence @ 90 nm technology to verify the proposed design.

A Monotonic Digitally Controlled Delay Element-Based Programmable Trigger Pulse Generator

This paper presents a resourceful utilization of a monotonic digitally controlled delay element (DCDE) to propose a programmable high frequency trigger pulse generator circuit (TPG). Performance evaluation of various analog and digital programmable delay elements (DEs) have been carried out to reach the conclusions presented. Further, this work exploits a monotonic DCDE along with an efficient XOR circuitry, to realize the proposed TPG. The proposed design generates a very high frequency ultra-thin pulses of pulse duration ranging from 56 to 170 ps for digital input vector ranging from ‘00000’ to ‘11111’, respectively. The proposed design has been extensively verified using SPICE @ 16-nm predictive technology model.

Investigating Phase Transform Behavior in Indium Selenide Based RAM and Its Validation as a Memory Element

Phase transform properties of Indium Selenide (In2Se3) based Random Access Memory (RAM) have been explored in this paper. Phase change random access memory (PCRAM) is an attractive solid-state nonvolatile memory that possesses potential to meet various current technology demands of memory design. Already reported PCRAM models are mainly based upon Germanium-Antimony-Tellurium (Ge2Sb2Te5 or GST) materials as their prime constituents. However, PCRAM using GST material lacks some important memory attributes required for memory elements such as larger resistance margin between the highly resistive amorphous and highly conductive crystalline states in phase change materials. This paper investigates various electrical and compositional properties of the Indium Selenide (In2Se3) material and also draws comparison with its counterpart mainly focusing on phase transform properties. To achieve this goal, a SPICE model of In2Se3 based PCRAM model has been reported in this work. The reported model has been also validated to act as a memory cell by associating it with a read/write circuit proposed in this work. Simulation results demonstrate impressive retentivity and low power consumption by requiring a set pulse of 208 μA for a duration of 100 μs to set the PCRAM in crystalline state. Similarly, a reset pulse of 11.7 μA for a duration of 20 ns can set the PCRAM in amorphous state. Modeling of In2Se3 based PCRAM has been done in Verilog-A and simulation results have been extensively verified using SPICE simulator.

CMOS based compact wide band tunable active inductor design

This paper presents a compendious architecture of an active tunable inductor with precise and wide tunability over its inductance value. Proposed tunable inductor requires only 3Ts (three transistors) to implement the design which reduces the transistor count as compared to 5Ts and 10Ts designs already available in literature. Broader range (35 GHz to 46 GHz) of linear operation with high quality factor (Q) is also obtained from the design presented. The achieved magnitude of impedance ranges from 2.6 KΩ to 6.1 KΩ for frequency variation of 25 GHz to 60 GHz. Further, maximum quality factor is obtained for input current of 62.3 μA. Apart from these, the proposed active inductor circuit is suited for high frequency operations up to 50 GHz. Further, this paper also compares the proposed inductor design with the designs already reported. The simulation results have been extensively verified using Virtuoso Analog Design Environment of Cadence Design System @ 45-nm technology node.

Revisiting performance of various delay elements to realize a trigger pulse generator

Various electronic circuits require a trigger pulse to initiate their operations. Circuits capable of producing very precise duration pulses can be utilized to trigger such circuits. Different designs of trigger pulse generator (TPG) circuit realized by employing optimal delay element (DE) and an XOR logic gate have been reviewed in this work. Profound study of programmable and non-programmable DEs (PDEs and NPDEs) have been also presented. These DEs can add a precise delay, mainly in the order of picoseconds, while passing a signal through it. Various design matrices such as duration of incorporated delays (pulse width) and its variability with supply voltages have been considered to evaluate the performance of the reported DEs. Further, this work is extended to realize a TPG circuit based upon the optimal DE found in this study. Based upon the utilized DE i.e. PDE or NPDE, two different realizations of programmable TPG (PTPG) and non-programmable TPG (NPTPG), have been reported. This work also reviews various reported design already available in literature to present a compact, low power, and high frequency TPG circuit. Delay element and XOR circuit are the key circuits for the TPG design presented. This work suggests various possible combinations of DE and XOR circuitry that will help the design engineers to choose an appropriate design based upon their requirements. Various design specification of the reported TPG circuit have been extracted to match with the different application specific requirements. The reported TPG circuit works with a very low supply voltage (700 mV) and proves its effectiveness by producing ultra-thin pulses of pulse duration in the order of ps while consuming minimal amount of power. The modeling of the TPG circuit have been done using predictive technology model (PTM) @ 16-nm technology node with Verilog and the simulation results are extensively verified using SPICE.