Rishab Mehra

A 2.5 GHz Low Power, High-

In this paper, a variation-aware and reliable design of a fully integrated radio frequency (RF) bandpass filter realized using a voltage differencing transconductance amplifier is presented. The filter is characterized by its high frequency operation, low power consumption, high quality factor, and it is insensitive to process, voltage, and temperature variations. Sensitivity analysis has been performed to analyze the circuit performance in the presence of parasitics. The inductor-less approach finds its application in integrated building blocks of RF front ends, thus eliminating the requirement of off-chip filters in transceivers. Centered at 2.511 GHz and operating within the 36.21 MHz 3-dB bandwidth, the filter draws 0.168 mA from a ±1 V power supply, attains a voltage gain of 72.6 dB, a quality factor of 69.34 and noise figure of ~29.6 dB. In addition, it has a dynamic range of 125.84 dB-Hz and a 1-dB compression of −1.5 dBm which translates into a figure of merit as high as 94 dB.

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This paper proposes a compact, low power high frequency trigger pulse generator circuit. Delay-introducing circuit that can incorporate a certain amount of delay during signal processing while maintaining the signal integrity is utilized in the proposed design. This paper evaluates performance of various delay-introducing circuits in terms of different design matrices. Further, this paper exploits the low power consuming delay element to implement the proposed trigger pulse generator. The proposed design generates very high frequency pulses at the cost of negligible power consumption. The effectiveness of the proposed circuit is presented by producing ultra-thin pulses of pulse duration 92.35 ps while consuming power of only 1.502 μW. Extensive simulations are carried out on SPICE @ 16-nm predictive technology model to verify the proposed design.

, Reliable Design of Active Bandpass Filter

An active inductor based on voltage differencing voltage transconductance amplifier (VDVTA) as an active element is presented. Using the active inductor, a bandpass filter is designed and the effect of process and current variations on the characteristics of the active grounded inductor-based bandpass filter is demonstrated. The bandpass filter shows its robustness against process and current variations. The simulation of the presented circuit is done using Virtuoso Analog Design Environment of Cadence @ 45-nm CMOS model parameters.

A Compact Low Power High Frequency Pulse Generator

This paper presents a resourceful utilization of a monotonic digitally controlled delay element (DCDE) to propose a programmable high frequency trigger pulse generator circuit (TPG). Performance evaluation of various analog and digital programmable delay elements (DEs) have been carried out to reach the conclusions presented. Further, this work exploits a monotonic DCDE along with an efficient XOR circuitry, to realize the proposed TPG. The proposed design generates a very high frequency ultra-thin pulses of pulse duration ranging from 56 to 170 ps for digital input vector ranging from ‘00000’ to ‘11111’, respectively. The proposed design has been extensively verified using SPICE @ 16-nm predictive technology model.

Process and Voltage Variation-Aware Design and Analysis of Active Grounded Inductor-Based Bandpass Filter

This paper presents a compendious architecture of an active tunable inductor with precise and wide tunability over its inductance value. Proposed tunable inductor requires only 3Ts (three transistors) to implement the design which reduces the transistor count as compared to 5Ts and 10Ts designs already available in literature. Broader range (35 GHz to 46 GHz) of linear operation with high quality factor (Q) is also obtained from the design presented. The achieved magnitude of impedance ranges from 2.6 KΩ to 6.1 KΩ for frequency variation of 25 GHz to 60 GHz. Further, maximum quality factor is obtained for input current of 62.3 μA. Apart from these, the proposed active inductor circuit is suited for high frequency operations up to 50 GHz. Further, this paper also compares the proposed inductor design with the designs already reported. The simulation results have been extensively verified using Virtuoso Analog Design Environment of Cadence Design System @ 45-nm technology node.

A Monotonic Digitally Controlled Delay Element-Based Programmable Trigger Pulse Generator

ABSTRACT In this paper, a multiple-input single-output (MISO) voltage-mode bi-quad active filter using voltage differencing voltage transconductance amplifier (VDVTA) is designed and analysed. The filter can realize several functions such as low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP). The proposed configuration employs three input voltages and generates a single output voltage. The filter characteristics, i.e., pole frequency (ωp) and quality factor (Q) are electronically tunable through the bias current of the VDVTA. The filter performance is analysed through sensitivity analysis in presence of parasitics as well as process, voltage and temperature fluctuations. The proposed design is implemented in a 45-nm CMOS technology and simulated using Virtuoso Analog Design Environment of Cadence.

CMOS based compact wide band tunable active inductor design

This paper primarily focuses on the power dissipation of cross coupled CMOS dynamic latches and also takes the technology scalability of the design into account. Mainly 3 topologies namely the Cascade Voltage Switch Logic (CVSL), Dynamic Single Transistor Clocked (DSTC) and Dynamic Ratio Insensitive (DRIS) have been investigated. A comparative study is provided which validates the suitability of the above latches for high-speed low power applications. Further, a brief account regarding the use of these latches for the design of high speed edge triggered flip-flops is also provided. The simulations results have been extensively verified on SPICE simulator using TSMC’s industry standard 180 nm technology model parameters and the technology scalability is tested with 22 nm predictive technology model developed by Nanoscale Integration and Modeling (NIMO) Group of Arizona State University (ASU).

Design and analysis of MISO bi-quad active filter

This paper presents an in-depth analysis of the propagation delay of dynamic CMOS latches and its variability when subjected to process, voltage and temperature (PVT) variations. Three basic topologies namely the cascade voltage switch logic (CVSL), dynamic single transistor clocked (DSTC) and dynamic ratio insensitive (DRIS) have been investigated for robustness and switching characteristics. The extensive analysis provides well-defined guidelines for selection of variation-aware CMOS latches used in digital logic design. All simulations have been performed on 180 nm TSMC industry standard technology node using SPICE circuit simulator.

Cross-Coupled Dynamic CMOS Latches: Scalability Analysis

This paper presents an in-depth analysis of NMOS capacitances across various technology nodes and device parameters which are extracted for different operating regions namely accumulation, cutoff, saturation and triode, while keeping the aspect ratio same for each transistor. Since MOS capacitances are the key parameters for estimating process development, material selection and device modeling, this paper enlists their variation with gate-to-source voltage (VGS) while keeping drain-to-source voltage (VDS) constant. This paper also aims to present the impact of capacitance variation on device performance that includes operating speed, power consumption, delay product and so on. The simulations results have been extensively verified using HSPICE simulator @ various technology nodes.

Cross-Coupled Dynamic CMOS Latches: Robustness Study of Timing

A voltage controlled tunable resistor (VCTR) with precise control over its resistance value, is reported in this paper. 6T based proposed VCTR design requires only six transistors, which reduces the transistor count as compared to 7T or 10T designs already available in the literature. Compact 6T VCTR design operates in the saturation region with a single control voltage. Presented design also mitigates the requirement of any additional bias current or voltage circuitry. This paper also validates the suitability of proposed 6T VCTR design for high frequency applications by employing it in a high-pass filter circuit. The simulations results have been extensively verified using Virtuoso Analog Design Environment of Cadence Design System @ 45-nm technology node.