Amitava Majumdar

Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies

A new industry-wide trend is the presence of multiple on-die power-supplies that are not directly connected to external supplies. Examples are internally-regulated supplies and power-gated supplies. This trend has brought to fore, the problem of testing for shorts between such internal supply grids and other (internal or external) supply grids. Today, presence of such shorts often results in excessive current draw from the tester and eventually results in burnt probe-tips adding to the overall cost of test. This paper proposes a classification of shorts defects involving internally regulated supplies. Two classes of solutions for mitigating or eliminating the problem are described. Methods for maximizing sensitivity of the solutions under leakage and probe-tip constraints are also described.

A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection

This paper presents a clock-less digital pulse stretcher which takes a short pulse as input and produces a detectable pulse that is longer than a required minimum duration. The proposed structure has high sensitivity to input pulse width and height and is capable of detecting deep sub-nanosecond pulses. This enables a wide variety of applications ranging from characterization of radiation-induced single-event transients to detection of glitch attacks and tamper resistance for security. Implementation of the proposed pulse stretcher in a 130nm process validates the analytical relationships between the input and output pulse. Simulation results show that the design can capture an input pulse with width larger than 50ps and height greater than 300mV. The shortest pulse that can be detected by the design can readily scale down with technology due to the digital nature of the circuitry.

Field profiling & monitoring of payload transistors in FPGAs

A new use for ring-oscillators (ROs) is proposed by which PMOS and NMOS transistor strengths can be measured and monitored in the field. A new metric, based on RO duty-cycle is defined. This new metric, along with RO-frequency, offers a way to profile and bin transistors based on their drive strengths. With ROs configured from payload transistors, along with the natural programmability of FPGAs, this strength based profiling can be done in the field at a level of granularity that is not possible with existing methodologies. New applications of the metrics and the profiling methodology include use of on-die ROs as a (a) monitor and control for duty-cycle sensitive designs, (b) replacement for scribe-line test structures, and (c) sensor for payload transistor characteristics over life-time.

Application debug in FPGAs in the presence of multiple asynchronous clocks

FPGAs have evolved rapidly over the past decade with a significant increase in size and complexity. Todays FPGA is indeed a system-on-chip (SOC) with a wide variety of hardened functionality, multiple asynchronous clock domains and widening interactions among different parts of the chip. It is commonplace to find applications that transfer data and control across clock-domains. This growing complexity, coupled with shrinking design cycles, has turned debug and verification into a critical design concern. Although software analysis tools have made significant progress over the years, this is not the case for debugging applications running on FPGAs. This paper describes a framework that enables non-intrusive application hardware debugging in the presence of multiple asynchronous clock domains. It offers full observability at minimal area and performance cost. The proposed approach uses Readback to retrieve the entire state of the circuit, a feature available in one form or another, in most commercial FPGAs today. Features such as single stepping and waveform reconstruction offer the same level of debug capability for applications accelerated on FPGAs, as simulation tools do for RTL implementations.

Innovative practices session 3C: Solving today's test challenges

Test vehicles are commonly used to understand the characteristics of a new process node. The ability to precisely identify and isolate defects is a key requirement during yield learning on these vehicles. Efficiently utilizing the fanouts in a design is critical to get a smaller pfa area. In this talk, we introduce the concept High Observability Patterns. High observability patterns target the detection of a defect in multiple patterns using multiple and different observe points. This allows the diagnostics engine to more precisely identify where the defect is and thus reducing the PFA area.

Hot topic session 9C: Test and fault tolerance for emerging memory technologies

Ever larger on-die memory arrays for future processors in CMOS logic technology drive the need for dense and scalable embedded memory alternatives beyond SRAM and eDRAM. Recent advances in nonvolatile spin transfer torque (STT) RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory. STTRAM exhibits scalable write current, sufficient read margin and nonvolatility or persistence, all of which make it an attractive solution for last level cache, embedded cache or even main memory. In an era of on-die non-volatile storage, new defect, disturb and fault mechanisms need to be comprehended during characterization as well as manufacturing tests. The first part of the talk will introduce STTRAM and review the fundamentals of the cell design, the read and write mechanisms as well as recent advances in technology, which make it a potential successor to eDRAM, followed by how variations and thermal noise limit the material and cell design space. The second part will discuss new test models that would be required for such non-volatile storage, the necessity of large scale data collection and analysis, as well as the need for BIST and on-line testing, and conclude with challenges and opportunities in STTRAM testing that lie ahead of us.

Innovative practices session 4C: Disruptive solutions in the non-digital world

Achieving automotive quality requires IC tests that achieve 100% coverage of potential defects. With new cell-aware digital test pattern generation techniques and the simple stuck-at fault model, this has proven practical for digital circuitry, but there is no equivalent for mixed-signal circuitry. A simple but realistic analog defect model is described, based on industrial observations and theory. It is consistent with previous proposals, but has novel differences that make it suitable for schematic and layout-extracted netlists and more efficient to simulate. A couple of examples show its effectiveness.