Raghunandan Chaware

Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

For the last few decades semiconductor industry has been following Moore Law effectively, which has resulted in significant miniaturization of transistors and on chip logic circuitry. Below the 28nm node, as design complexity of the IC (Integrated Circuits) increases, cost and risk associated with these designs are becoming prohibitive for many companies. Three dimensions (3D) die stacking methodology offers unique advantages of low power and high bandwidth per watt without increasing the cost significantly. For FPGAs (Field Programmable Gate Array), stacked silicon integration (SSI) technology offers a cost effective solution to build large die with very high logic cell count. In order to create a larger FPGA, four different 28nm FPGA die are connected to each other through a 65nm passive silicon interposer. The FPGA die are connected to interposer through micro-bumps (ubumps). This paper describes the technical challenges associated with 3D integration of 100um thin interposer and FPGA die on to a package and stacked die package reliability. The assembly test vehicle was comprised of four 28nm chips mounted side by side on a 25 mm × 31 mm 100um thick interposer with thousands of micro-bumps at 45um pitch. This top die and interposer stack was assembled on a 35mm × 35mm and 45mm × 45mm package with 180um pitch C4 bumps. Several assembly experiments were performed to compare performance of mass reflow assembly and thermo compression bonding assembly to join top FPGA die with ubumps. Assembly yield and reliability were used as two main criteria in deciding the best assembly process. Micro-bump resistance was monitored by Through Silicon Via (TSV) chains, Kelvin bump structure and daisy chains in order to check interconnect integrity after assembly and during reliability testing. After assembly evaluations, separate underfill screening design of experiment (DOE) was performed to choose the best underfill candidates for reliability evaluations. Reliability evaluations were performed with best underfill candidates and parts were subjected to L4 preconditioning and -55°C to 125°C thermal cycling. Parts were subjected to extended thermal cycling, i.e. beyond 1000 cycles, to understand the other possible failure modes. Assembly evaluations showed that the choice of the assembly process was strongly dependent on the die size, interposer design and interposer process. Choice of flux also affected the ubump assembly yield and underfill flow. Underfilling experiments confirmed that optimization of underfill process required optimization of dispense pattern, ubump parameters. Reliability evaluations showed that the reliability was affected by choice of underfill, interposer cleaning, and die thickness/package structure. One of the common failure modes was delamination between interposer and C4 underfill.

Assembly process integration challenges and reliability assessment of multiple 28nm FPGAs assembled on a Large 65nm passive interposer

Stacked die packaging has been gaining traction in recent years due to cost and manufacturing issues associated transistor scaling. 3D die stacking architecture with through silicon vias offers a unique combination of low power and high bandwidth per watt without increasing the cost significantly. For Xilinxs FPGAs (Field Programmable Gate Array), due to its repetitive and unique structures, Stacked Silicon Integration (SSI) technology becomes a perfect fit to provide a cost effective solution to build large programmable logic devices with very high logic cell count. In the current configuration, four separate 28nm FPGA die were connected to each other through a 65nm passive silicon interposer. Arrays of more than 10k micro-bumps (ubumps) stitched these four dies together through the silicon interposer. This paper describes the technical and reliability challenges associated with 3D integration of 100um thin interposer and FPGA die on to a single package.

A comprehensive reliability study on a CoWoS 3D IC package

Assembly of stacked die side by side on a passive interposer enables high-bandwidth connectivity between multiple die by providing a significantly large number of die to die connections that otherwise are not possible in a multi-chip-module (MCM) configuration. It also provides much lower latency and consumes dramatically lower power than either the multiple FPGA or MCM approach. This enables integration of massive quantities of interconnect logic, transceivers, and on-chip resources within a single package. However, this also poses critical challenge of testing the reliability of inter die connections during board level testing. Traditionally, flip chip reliability evaluations use independent component and board level methods to capture various failure modes. The board level method is often a simple daisy chain test method that targets the Ball Grid Array (BGA) solder balls. The component level test captures the C4 and active circuitry but ignore BGA and the effect of board mounting assembly process. Given complexities in terms of geometry, material and assembly process, 3D IC packages are more sensitive to warpage changes. Small changes in warpage can have a significant reliability impact on the thin interposer as well as the stacked silicon. A unified test methodology that can test the top FPGA die, inter die interconnections, TSV, C4 bumps and BGA connections while being mounted on a board is the most comprehensive method for performing reliability evaluations on a 3DIC package, much like an end user/customer would see in their application. This paper presents a novel methodology and results of a comprehensive functional board level reliability evaluation on a 3D IC package assembled using Chip on Wafer on Substrate (CoWoSTM) process. The comprehensive reliability evaluation method discussed in this paper uses a specially designed test board for mounting the functional device. The test board much like a probe card provides access to active circuitry in the stacked silicon. This enables identifying any small silicon crack , Low-K delamination or degradation in the active silicon. Additionally the test board also provides access to 85000 die to die microbump interconnections. Having access to the microbump is very important as they form 80% of the interconnections and more susceptible to failure due to their geometry and material complexities. Finally, all other general purpose IOs can also be tested much like a daisy chain board level vehicle. The reliability of the CoWoS 3DIC device mounted on the board was tested for various high temperature storage and thermal cycling test conditions for beyond JEDEC requirements. The comprehensive test methodology was effective in capturing various failure modes and their interactions. The results of this study have clearly demonstrated the robustness of the CoWoS 3D IC device. The packages and FPGA die survived extended tests well beyond the JEDEC test requirements.

Assembly challenges in developing 3D IC package with ultra high yield and high reliability

As the size and complexity of the designs grows larger, Field Programmable Gate Array (FPGA) based design solutions are becoming more dominant in system designs due to their ability to offer higher logic capacity and more on chip resources. FPGA based design solutions that offer higher capacity and higher bandwidth with low latency and power can provide system level functionality similar to Application Specific Integrated Circuits (ASICs). Stacked die technology enables high bandwidth connectivity between the multiple die by providing significantly large number of connection via microbumps. This interposer based die stacking approach provides low power and latency, but also adds manufacturing complexity. Any assembly process technology is viable only if it is manufacturable with high yields. This paper discusses key challenges observed during manufacturing of 28nm 3DIC products with CoWoS™ (Chip-On-Wafer-On-Substrate) process. During the initial product ramp stage, most of the failures observed were related to interposer level assembly process. Common failure modes were ubump opens, interposer metal line opens and shorts, interposer metal line shorts and TSV to C4 opens. Specific isolation patterns were developed to isolate the interconnect failure to single ubump. After identifying the ubump, the failure was verified with failure analysis. The failure was then mapped on the interposer wafer and analyzed for any inline process deviations. With such close loop feedback process, this problem was resolved quickly to provide very stable and high yielding interconnection process. Another unique failure mode observed during assembly was transistor damage caused during 3DIC assembly. In order to identify the root cause and isolate the problem, different assembly process splits and process corner studies were performed. A C4 probe card was designed to provide an intermediate test point at a major process loop after wafer level die assembly and before flip chip assembly of the stacked die on the organic package. The results of the intermediate probing suggested that multiple process steps could be contributing to this type of failure mode. Failure isolation was performed by post processing of final test data. With specialized isolation patterns, the failure locations were mapped on the interposer wafers and the FPGA wafer. Results suggested that wafer fab process changes did not have an impact on the failure mode and transistor defects were introduced during integration and assembly of FPGA die on the interposer wafer. Series of assembly improvements implemented in the assembly process will be discussed in the paper. The process improvement qualification was completed by subjecting the parts to temperature cycling and high temperature storage (HTS) tests. Extended temperature cycling tests were performed and the parts were subjected to Level 4 preconditioning followed by 1500 cycles of -55°C to 125°C temperature cycle condition. Evaluation units were also subjected to 4000 hours of HTS. All the parts successfully passed the extended reliability evaluations.

Assembly process qualification and reliability evaluations for heterogeneous 2.5D FPGA with HiCTE Ceramic

This paper presents results for assembly and reliability evaluations performed while developing a first of its kind heterogeneous 2.5D HiCTE Ceramic Field Programmable Gate Array (FPGA) package. The heterogeneous device discussed here is a three dimensionally stacked FPGA device integrated with a 28G Transceiver die using a passive interposer. Several thousands of micro bumps are used for making connections between the FPGA die slices and the 28G transceiver through a passive interposer. Such heterogeneous integration enables ultra-high inter-die bandwidth and capacity at very low power that are essential for meeting the growing demands in the communication space. Also, it helps in achieving a much lower latency. The selection of ceramic substrates makes this three dimensional stacking very unique as its behavior at high temperature is very different from its organic counterparts. The Assembly test vehicles comprised of two 28nm FPGA Die and one 28nm Transceiver Die, all stacked side by side on a 25 mm × 20mm interposer. The FPGA and Interposer assembly was stacked on a 35mm × 35mm Ceramic Substrate with 180μm pitch C4 bumps. Assembly evaluations were primarily focused on qualifying various materials and assembly processes to enable a heterogeneous stacked silicon assembly on a ceramic substrate. Micro bump joint quality, assembly yield, component level reliability and board level reliability have been used as the key gating items for this process qualification study. Two different assembly processes, namely thermo-compression (TC) bonding and mass reflow, were compared during this evaluation. Component and board level reliability evaluations were carried out for various assembly and material combinations. The assembled units were subjected to Level 4 (L4) preconditioning test followed by -55°C to 125 °C thermal regimes and tested for functionality to monitor the component level reliability. Board level studies were conducted at 0°C to 100 °C using daisy chain substrates. The resistance of the BGA chain was used for monitoring the board level reliability. The results of this evaluation have clearly demonstrated a strong interaction between the materials, assembly process and reliability. The choice of the assembly process was observed to have a significant impact on the micro bump joint quality. However, the choice of the assembly process itself was dependent on the selection of the various assembly materials including underfill, flux, substrate type, surface finish, lid thickness and die thickness. The assembly process and material set together influenced the component and board level reliability significantly.

Reliability improvement of 90nm large flip chip low-k die via dicing and assembly process optimization

Increasing demand for higher processing speeds and enhanced electrical performance have made the use of low-k dielectric materials mandatory. For such low-k dielectric materials, enhanced dielectric properties are achieved via increased porosity of the low-k materials. These new low-k materials have different chemical, thermal, and mechanical properties than traditional dielectric materials used in older silicon technology, which in turn creates integration issues. The adhesion of the low-k layers in the silicon is also relatively weak. Due to their poor adhesion and brittle nature, low-k materials have a tendency to crack and chip during mechanical dicing with diamond blades, a widely used die singulation technique. In the case of field programmable gate array (FPGA) chips, as the demand for higher speeds and enhanced functionality increases, the size of the flip chip die grows accordingly to offer higher number of logic cells. Large flip chip die also requires a large package for efficient signal routing. Consequently, the stresses generated due to thermal expansion mismatch are severe, and even a small defect created on the edge of the chip during the dicing process can have a severe impact on the reliability of the flip chip device. To study the impact on flip chip reliability, two different laser dicing technologies were compared with the conventional mechanical dicing process. Other important variables tested during this study were dicing location in the saw street, lid attach dispense pattern, wafer lots, die size, and underfill. Reliability analysis indicated that for improvement of the reliability of the samples diced with mechanical dicing process, correct choice of underfill and lid attach material, optimization of the lid attach dispense pattern, and optimization of dicing location were required. In contrast, a wide reliability and process window was achieved by laser grooving process and none of the above factors tested during the study had any impact on the reliability.

Reliability Evaluations on 3D IC Package beyond JEDEC

3DIC technology has enabled scaling beyond the Moores Law to achieve higher transistor count, increased functionality and superior performance. Additionally, this technology allows integrating heterogeneous components such as Processor, FPGA, GPU, Memory, Serdes, etc. on the same interposer die enabling faster computing through reduced latency. The yields on the 3DIC technology have matured and are equivalent monolithic flip chip products. All of the above has made 3DIC technology the key driver for some of the high end computing applications such as Data centers. Any technology is viable only if the end product is reliable and manufacturable with high yields. Understanding the reliability margin of 3D IC package is essential for making them commercially successful. Standard product qualification tests use JEDEC test standards for qualifying the product before ramping into mass production. This might be enough for standard flip chip and wirebond technologies, which have been deployed in the field for many years and the failure modes and acceleration factors are well understood. However, in 3D IC technology, both the assembly process and the assembly materials are new and evolving. Small variations in the process parameters or variations in material concentrations could have significant impact on the reliability. A comprehensive reliability study including component, board and system level is therefore very essential to capture interactions due to process and material variations and material interactions. This paper will compare the results of an extended reliability test evaluation for 3D IC package. This extended reliability study utilized a component level test vehicle, functional board level test vehicle and power cycling test vehicle for comprehensive understanding of the reliability margin. The component level tests followed the standard qualification practice. The functional reliability test set up used specially designed board to test the system level reliability. The functional test vehicle much like a probe card provides access to active circuitry in the stacked silicon, ubumps and C4 bumps while being mounted on the board. This enables replicating the component level tests on a board level. The power cycling tests were performed by utilizing the same functional board test vehicle and special software patterns were implemented to perform power cycling. Special software patterns were designed to heat the device and control the fan for cooling. This study has compared the extended reliability of multiple 3DIC devices with interposer sizes starting from 24mm and extending upto 36mm which is beyond the size of the standard reticle. Also, this study has compared the extended reliability of 3D IC package with eutectic and copper pillar C4 bump. The reliability tests have been conducted on multiple lots over time as an extended reliability monitor to capture process variations. The extended tests have been critical in finding process and material defects critical for improving the overall reliability margin of the 3D IC device.

Overmolded flip chip packaging solution for large die FPGA with 65nm low-k dielectrics

Flip chip ball grid array (FGBGA) packaging is widely used for high performance devices that require high pin count and enhanced electrical performance. However, current standard flip chip package construction has difficulties in meeting package coplanarity requirements for large packages, especially with thin core substrates. Moreover, due to concerns with corrosion of exposed passive components, standard flip chip package construction with lid is not suitable for applications in which harsh cleaning solvents are used during board assembly. The utilization of low-k in the silicon to enhance device performance presents additional challenges to component reliability. In order to address these concerns, a molded FCBGA package was developed for large die (∼23 mm2) devices. In the molded flip chip package, the die is underfilled as well as overmolded. This overmolded structure provides good package coplanarity, protection from harsh environments, and structural support for thin substrates. It also offers good bump protection and improves board level reliability. During this study, three different mold compounds were tested with 65nm and 90nm low-k test vehicles with die sizes greater than 21 mm. Effect of different factors such as substrate solder mask, die size, and molding compound properties on the assembly and reliability was studied during these evaluations. This paper also discusses other assembly process related factors that can impact the reliability of the molded flip chip package with large low-k die and large packages. The study shows that the molded FCBGA structure improves the warpage of large packages and can provide good reliability performance for large die with low-k dielectrics. These results also indicate that molded flip chip, which employs high modulus mold compound to give low warpage, could be a potential solution for lead free flip chip packages.