Amparo Herrera

A 4.5 GHz 3-4 dual-modulus frequency divider IC in GaAs technology

This paper presents a divide-by-3/divide-by-4 dual-modulus frequency divider fabricated in a commercially available GaAs pHEMT technology. The highspeed architecture presented overcomes the inherent frequency limitations of the classical Johnson structure and allows the same speed of the simple divider-by-4 circuit from which it derives. Even if the circuit was designed specifically for its use in frequency generation modules of satellite transponder, it can be conveniently used as the first stage of high frequency dual-modulus prescalers. The fabricated circuit operates up to 4.5GHz with a total power consumption of 75mA from a 3.5V supply.

Tunable integrated output impedance transformer on a power amplifier for 4G applications

This paper presents the design of a modified Ruthroff-type transmission line transformer with tuning capability. The variation of a capacitor included in the structure allows the output impedance of a power amplifier to be changed in order to prevent degradation of the efficiency due to changes in the needs of the amplifier load produced by variations in the fabrication process. The impedance transformer integrated with a WCDMA power amplifier implemented in CMOS technology has been measured obtaining high efficiency, with values of 44.7 % and 43.3 % despite the load variation and an output power of 28.9 dBm and 28.7 dBm for two different chips.

ESD structures impact analysis on a WLAN 802.11a LNA

This paper presents a MMIC ESD protected low-noise amplifier manufactured in SiGe:C BiCMOS technology for the IEEE 802.11a/HiperLAN WLAN standard. The LNA operates at 5.2 GHz and achieves a measured gain of 22 dB, a noise figure of 3.3 dB and an output 1 dB compression point of -3 dBm. The amplifier also shows wideband input and output matching The ESD protection circuit has been modeled and the results have been used to study its impact in the performance of the amplifier. The LNA was mounted and measured to test the similarity with simulations.

First run S-DMB MMIC low noise amplifier

This paper reports on the simulation steps needed to design a GaAs MMIC LNA for S-DMB on-board satellite applications in only one fabrication iteration, which achieves a noise figure <; 1.3 dB and gain> 28 dB for applications from 1.95 to 2.3 GHz. In addition, the amplifier obtains a high linearity with an OIP3 of 20.7 dBm and PldB of 6 dBm over a 1.95-2.3 GHz bandwidth. Availability of accurate library simulation models and the use of ADS co-simulation scheme permit us reducing design time and more importantly obtaining a first run working chip.

CMOS VCO design optimization using reliable 3D electromagnetic inductor models

Lack of reliable inductor models at high frequencies in SiGe makes the design of certain microwave circuits a tiresome task. This paper presents the design process of a fully integrated 11.6 GHz BiCMOS VCO with a good compromise between phase noise, power consumption and area. Inductors are essential components in the VCO design and therefore must be carefully modeled. We propose the use of a three dimensional electromagnetic field simulator to characterize the silicon integrated planar inductor within the VCO. Simulation and measurement results demonstrate how the use of an accurate inductor model can significantly reduce the designing steps leading to a first time working silicon.

Ranging and Communications with Impulse Radio Ultrawideband

This paper describes the design and development of an Impulse Radio Ul-trawideband demonstration platform, in order to evaluate and test the performance of UWB technologies for future advanced smart networking. The whole architecture is described, covering both hardware and software implementation, together with the Time of Arrival (ToA) ranging technique applied, and the achieved results. As a main output of the work performed, the first conclusion is that UWB technologies can be employed in order to perform accurate ranging estimations below 1 m, without heavy and costly signal processing on the nodes. The work described in this paper has been carried out in the scope of the FP7 Where Project.

Dual band monolithic AGC amplifier for space applications based on a commercial 0.2 /spl mu/m PHEMT technology

This paper reports the design and measurement of a dual band monolithic AGC amplifier to be used in transmit/receive modules for Telemetry, Tracking and Control (TTC) of satellite systems. The amplifier is also included in a multifunction Monolithic Microwave Integrated Circuit, MMIC, containing frequency converters. The block diagram of this chip is shown in figure 1. The goal of the work is to reduce the number, size, and consequently, the cost of the circuitry actually in use, whilst maintaining performance, through the use of mature GaAs PHEMT technology. Issues such as circuit topologies, dc power consumption, circuit area minimization and optimization are all important factors that are addressed during the design.