Amr M. Lotfy

A novel digital loop filter architecture for bang-bang ADPLL

Bang-Bang Phase Locked Loops (BB-PLLs) exhibit a nonlinear response that is dependent on the magnitude of the phase error. This paper presents a novel Digital Loop Filter (DLF) with coefficients that adapt to the relative magnitude of the phase error, and hence, enhances system linearity. An All-Digital BB-PLL (BB-ADPLL) that incorporates the proposed DLF is implemented using 32nm technology. AMS simulations are used to demonstrate the impact of the proposed DLF on the system linearity. Furthermore, theoretical analysis indicates 75% enhancement in the linearity of the proposed system compared to conventional DLFs.

A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO

A hybrid Time to Digital Converter (TDC) — Bang Bang (BB) All Digital Phase Locked Loop (ADPLL) architecture is proposed to optimize power, area, lock time, and design complexity. The Hybrid ADPLL architecture utilizes a low resolution two synthesizable Time to Digital Converters to achieve fast lock time, and then switches to a Bang-Bang like architecture once it is in the locked state. Such hybrid architecture enables the ADPLL to achieve lock time in less than 1 μ sec using an adaptive proportional derivative digital loop filter while consuming a power of 5.1 mW when locked at 4GHz with 1.37 ps rms period jitter. Additionally, The proposed ADPLL utilizes a novel power gated digitally controlled oscillator to power minimum number of transistors once the ADPLL is locked in a specific frequency band. The ADPLL occupies a total area of 85×150 μm2 when synthesized on TSMC 65nm.

A novel power gated digitally controlled oscillator

In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70∗70 μm2. The phase noise of the free running DCO is −92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency.

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology

This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The proposed model exploits the sampled nature of the PLL where most of its analog behavior takes effect during the phase detection, and remains almost constant during the rest of the reference cycle. The PLL model simulation run time takes only 1 second, which makes it a perfect fit for pre-silicon digital validation as well as top-down design methodology. Compared to transistor-level Spice simulations, the proposed model shows a correlation of more than 97% for the PLL locking behavior, jitter, and phase noise. The PLL model is used to exercise critical features like spread-spectrum clocking (SSC) and adaptive frequency system (AFS). In addition, the model was integrated in a pre-silicon validation environment and enabled catching design bugs.

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter

This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between stability and jitter of a closed loop. A proposed simple digital controlled oscillator (DCO) based on three stages ring oscillator provides a wide frequency range, and proven to be of lower area and power compared to arrayed DCO. The proposed design results in a significant reduction in the area and power compared to other time-to-digital converter (TDC) based ADPLL architectures. This reduction results from eliminating the need for complex, power, and area consuming TDC block, and arrayed DCO. A counter-based frequency acquisition loop using a binary search algorithm reduced the lock-in time significantly compared to similar work. The proposed BBADPLL architecture was implemented on TSMC CMOS 65nm technology with a frequency range 5–10GHz and a frequency resolution equals to 500MHz. The lock-in time is 2.4µs. The peak-to-peak period jitter and the RMS jitter at 10GHz are 1.49ps and 0.19ps, respectively. The total power consumed at 10GHz is only 2.7mWatt and the total area of the proposed ADPLL is 4372µm2, which is very small compared to other published architectures.

Modeling the response of Bang-Bang digital PLLs to phase error perturbations

Bang-Bang phase locked loops (BB-PLLs) offer a low power implementation of digital PLLs. However, the response of BB-PLLs, unlike linear PLLs, depends on the magnitude of the phase error, and thus, exhibits hard nonlinearity. This paper presents a generic modeling methodology for digital BB-PLLs in the locked state using simple time domain analysis. The proposed model predicts the response of BB-PLL to a given phase error magnitude in terms of stability (maintaining lock), and settling time (relock time). The model further aids the design process by providing insight for the system response in terms of the loop parameters. An example BB-PLL system is implemented in 32nm technology, and the proposed model is applied. Verified by analog-mixed signal (AMS) simulations, the model was successful in predicting the system response, and indicating stability and settling time of the system for a given phase error magnitude.