Greg Taylor

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.

Enhancing microprocessor immunity to power supply noise with clock/data compensation

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show through extensive analysis techniques that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on 130- and 180-nm processors validate the approach.

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping

The impedance of a microprocessor power-delivery network peaks at ~140MHz, resulting in power-grid resonance, which lowers operating frequency and compromises reliability. A suppression circuit uses an active-damping technique with a maximum of 12.7dB peak-to-peak noise reduction from 70 to 250MHz in a 90nm CMOS process.

On-die clock jitter detector for high speed microprocessors

An on-die clock jitter detector has been designed for high speed microprocessor circuits and fabricated in 0.18 /spl mu/m CMOS technology. Variation of internal clock high/low time or period has been recorded. Innovative circuit techniques are used to provide fast initial DLL lock, adaptive filtering, granular jitter computation, and enhanced immunity to power-supply noise. It compares individual clock cycles to the average clock period, reporting the differences. The system has multiple output modes to allow more complete understanding of the jitter distribution and time dependence.

2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS

An all-digital True Random Number Generator is fabricated in 45nm CMOS with 2.4Gbps random bit throughput and total power consumption of 7mW. Two-step coarse/fine-grained tuning with a self-calibrating feedback loop enables robust operation in the presence of 20% process variation while providing immunity to run-time voltage and temperature fluctuations. The 100% digital design enables a compact layout occupying 4004µm2 with measured entropy of 0.999965, and scalable operation down to 280mV, while passing all NIST RNG tests.

Design and validation of a power supply noise reduction technique

For the high-performance microprocessors with high-bandwidth I/O, the power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high-quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). In this paper, we will present two implementations of an approach of using on-die resistors in series with the package capacitance to dampen the high-frequency noise. We will show by validation on the 90-nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings. The results of several validation experiments, including the measurement of noise and impedance of the I/O power delivery, and the post-layout simulation will also be presented.

Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery

In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal layer usage control for intra-block-level routing, (3) dual-Vth design, and (4) functional unit block (FUB) folding. With aforementioned methods combined, our 2-tier 3D designs provide up to 52.3% reduced footprint, 25.5% shorter wirelength, 30.2% decreased buffer cell count, and 21.2% power reduction over the 2D counterpart under the same performance.

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS

In the multicore era, thermal/power management is essential in order to meet platform-performance and energy-efficiency requirements. Accurate temperature measurements are required to reliably maximize microprocessor performance under a thermal envelope. Furthermore, in a large multicore microprocessor, multiple-location hot-spot temperature measurements are critical to limit leakage through load balancing. The requirements for absolute inaccuracy are modest (≪8°C), but good relative inaccuracy (≪3°C) is needed [1,2]. Increases in transistor variations and switching noise make static measurements difficult, and having multiple local temperature sensors for each hot-spot location is impractical. Besides, trimming a sensor for each hot-spot is costly. This paper presents a temperature sensor for remote temperature sensing that achieves the required resolution and variation tolerances by: 1) chopping the input current to the remote BJT pair; 2) deriving a voltage reference from the same BJTs; 3) making multiple current ratio measurements to eliminate parasitic resistance; and 4) using digital demodulation to eliminate analog offsets.

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Traditional inaccuracies during manufacturing test of the thermal sensor circuit require excessive guard-bands. These guard-bands increase the chance of unnecessary microprocessor throttling and could introduce a less-than optimum power and thermal design envelope. Circuit techniques that minimize these errors are discussed, including an improved temperature-independent voltage pump, a remote thermal sensing scheme for hot-spot to sensor offset reduction, and a self-heating error calibration method. Experimental data obtained on a high performance 65nm Intel® Pentium® 4 microprocessor demonstrates the feasibility and effectiveness of these techniques, providing a combined potential accuracy improvement of up to 17°C.