Amy J. Moll

Polymer thickness effects on Bosch etch profiles

Time-multiplexed etching, the Bosch process, is a technique consisting of alternating etch and deposition cycles to produce high aspect-ratio etched features. The Bosch process uses SF6 and C4F8 as etch and polymer deposition gases, respectively. In these experiments, polymer thickness is controlled by both C4F8 gas flow rates and by deposition cycle time. The authors show that polymer thickness can be used to control wall angle and curvature at the base of feature walls. Wall angle is found to be independent of trench width under thin-polymer deposition conditions. Experimental results are compared to results obtained by other researchers using the more conventional simultaneous etch/deposition technique.

Thermo-mechanical characterization of copper through-wafer interconnects

Copper through wafer interconnects (TWIs) have become a viable solution to providing interconnectivity between stacked die. In a world where minimizing chip real estate while increasing functionality is the goal for further miniaturization of electronics, TWIs hold a key role as new packaging schemes become critical for overall higher density. Little is known, however, about the impacts of mismatched coefficients of thermal expansion (CTEs) inherent to the materials used in their construction. CTE differences, if left unresolved, can pose reliability issues during TWI operation. This research focuses on providing insight into the stress levels experienced by TWI materials through finite element analysis to gain a better understanding of the possible failure mechanisms associated with the CTE differences

Energy scavenging device in LTCC materials

Energy scavenging devices can use environmental vibrations to power remote devices without the need for wires or batteries. This paper discusses the use of low temperature co-fired ceramics to design and fabricate a compact, multilayer coil to power an electromagnetic energy scavenging device

Integrating Through-Wafer Interconnects With Active Devices and Circuits

Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.

Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics

Circuit-level oxide degradation effects on CMOS inverter circuit operation and individual MOSFET behavior is investigated. Individual PMOSFET and NMOSFET devices are assembled off-wafer in the inverter configuration through a switch matrix. A range of gate oxide degradation mechanisms are induced by applying a ramped voltage stress (RVS) of various magnitudes to the input of the inverter. A novel circuit model is used to simulate the voltage transfer curves (VTCs) of degraded inverters. At the transistor level, increased gate leakage currents of nearly eight orders of magnitude are observed, in addition to severely reduced on-currents (> 50 percent reduction), and large threshold voltage (V/sub th/) shifts (> 100 mV). At the circuit-level, stress of either polarity results in inverter performance degradation. For the DC characteristics, oxide degradation attributed to limited hard breakdown (LHBD) in the NMOSFET and hard breakdown (HBD) in the PMOSFET, results in decreased output voltage swing (> 260 mV). Under the same conditions, inverter degradation in the voltage-time (V-t) domain exposes much larger changes in performance. For instance, significant increase in the rise time results in the output voltage being pulled up to only 660 MV (V/sub DD/ = 1.8 V) before switching low. From a circuit reliability viewpoint, it may be possible for subsequent circuit stages to compensate for a few degraded devices, but in highspeed circuits, increased rise/fall and delay times may cause timing issues. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages or result in increased power consumption.

Effects of circuit-level stress on inverter performance and MOSFET characteristics

The effects of circuit level-stress on both inverter operation and MOSFET characteristics have been investigated. Individual MOSFETs, with gate oxide thicknesses of 3.2 nm and active dimensions of 25/spl mu/m /spl times/ 25/spl mu/m, are connected in an inverter configuration off-wafer via low-leakage switch matrix. Inverters are stressed with a ramped voltage stress (RVS) of various magnitudes to induce different degrees of gate oxide degradation. In addition voltage transfer curves (VTCs) of degraded inverters are simulated using a new circuit model. AT the transistor level, both the PMOSFET and NMOSFET show increase gate leakage current up to eight orders of magnitude, severely reduced on-currents and transconductance (g/sub m/), and large threshold voltage (V/sub t/) shifts of 100 mV or more. Different trends in inverter performance are observed following positive and negative stress. However, regardless of stress polarity, circuit-level stress results in inverter performance degradation, such as reduced output swing, switching point shifts, and increased rise/fall times. After the largest positive RVS, the output voltage swing has decreased from 1.8 V fresh, to 1.54 V post-stress. Much larger changes in the inverter voltage (V-t) time domain performance are observed. The minimum output low voltage is similar to that of the VTC, but the rise time increase significantly enough that the output voltage is only pull up to 660 mV (V/sub DD/=1.8V) before it switches low. In terms of circuit reliability, it maybe possible for subsequent circuit stages to compensate for a few degraded devices, but increase rise/fall and delay times may cause timing issues in high-speed circuits. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages or result in increase power consumption.

A Stackable Silicon Interposer with Integrated Through-Wafer Inductors

Three-dimensional (3-D) device stacking technologies provide an effective path to the miniaturization of electronic systems. These 3-D stacks can be envisioned to contain, in addition to active device layers, interposers with passive devices. The stackable interposer concept is compatible with any integratable passive device architecture, but is particularly well suited to 3-D enabled passives which take advantage of the bulk of the layer and the connectivity on two surfaces. In this paper we report on the design, fabrication and electrical characteristics of a 3-D enabled solenoidal inductor.

Electrical characterization of through-wafer interconnects

Through-wafer interconnects (TWI) allows 3-D chip stacking enabling integration of multiple chip functions (i.e. opto-electronic, analog or digital) with reduced power and space requirements. To date, non-destructive characterization techniques for determining interconnect integrity and reliability have not been developed. This work examines a specially modified electrical four-point probe for non-destructive characterization of TWIs. Technical challenges and measurement optimization methods are reported.

Through wafer interconnects on active pMOS devices

The objective of this research is to demonstrate the ability to create through-wafer interconnects (TWIs) on wafers with active devices. TWIs have previously been demonstrated on blank Si wafers. The application of TWIs in an industrial setting requires no damage or yield loss to the existing devices during additional processing steps. The test vehicle chosen is a simple pMOS test chip, which includes different structures such as transistors and invertors. The processing steps and sequence required to integrate TWIs into wafers with active devices is demonstrated.

Microstructural Effects during Chemical Mechanical Planarization of Copper

Die-stacking schema using through-wafer interconnects require vias to be filled with electroplated Cu, resulting in thick copper films and requiring an aggressive first-step chemical mechanical planarization (CMP). This work investigates the effects of microstructure on CMP of copper films, which are not presently well understood. Bulk and local removal rates are investigated for several different microstructures. Surface orientation maps are created, and the orientations of individual grains are correlated with topographical data to elucidate local removal behavior. Cu removal depends on the details of the microstructure, and certain microstructures allow for either faster or more uniform removal of thick Cu films.