An Pan

An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes

The quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power. The architecture implements the normalized min-sum algorithm, rearranges the original two-phase message-passing flow, and adopts an efficient quantization method for the second minimum absolute values, an optimized storing scheme for the position indexes and signs, and an elaborate clock gating technique for substantive memories and registers. It is also configurable for any regular and irregular QC-LDPC codes, and can be easily tuned up to different code rates and code word lengths. The chip is fabricated in an SMIC 0.18- six-metal-layer standard CMOS technology. It attains a throughput of 104.5 Mb/s, and dissipates an average power of 486 mW at 125 MHz, and 15 decoding iterations. The core area is only 9.76 mm2. The chip has been applied into the China digital terrestrial/television multimedia broadcasting system.

Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond

A programmable architecture is proposed for a flexi-mode quasi-cyclic low-density parity-check code decoder. The proposed architecture has the following advantages: 1) Code rate, length, and pattern can be programmed on the fly; 2) decoding complexity is reduced by algorithm modification; 3) memory read/write operation is reduced by access optimization and hierarchical memory structure; and 4) an early stopping scheme is adopted to give power efficiency, particularly in the low-signal-to-noise-ratio region. A decoder chip is implemented in an SMIC 180-nm 1.8-V CMOS technology. Experimental results show the advantages in terms of flexibility, area, power, and error-correction performance.

Low-cost reconfigurable VLSI architecture for fast fourier transform

In this paper, a low-cost reconfigurable FFT processor employing novel dual-path pipelined shared memory architecture is presented. Based on this architecture, an elaborate memory configuration scheme is designed to make single-port SRAM available. Moreover, a mixed-radix butterfly unit is also designed, which makes the processor capable of multimode operation. Compared with previous ones, the proposed architecture can greatly reduce area. In addition, an optimized data scaling approach is proposed and the signal-to-quantization noise ratio (SQNR) of an 8K-point fixed-point FFT can achieve 52.7dB with the wordlength of 13bit. A test chip for DVB-T/H is implemented with the proposed architecture and fabricated in 0.18-mum single-poly six-metal CMOS process. The core area of this chip is 2.83mm2 with the power dissipation of 25.8mW at 20MHz.

A power and area efficient architecture of convolver based on ram

This paper proposes a novel architecture of the convolver which can also be used as a correlator (depend on the order in which the input sequence are put in). It is power and area efficient compared with the typical architectures based on registers. Two groups of convolver are implemented to show the improvement. One group deals with two 12bit data sequences of length 64, while another deals with two 12bit data sequences of length 256, with each group containing a ram based one and a conventional one. The synthesis results by DC using SMIC 0.13um library and the results of Prime Power shows that in the second group, the area and power of the ram based one can be reduced to 91% and only 77% of the conventional one, respectively.1

A 179-mW 2304-bit flexible LDPC decoder for Wireless-MAN applications

A 2304-bit flexible decoder for low-density parity-check (LDPC) codes is presented for Wireless-MAN applications. Based on modified turbo-decoding message-passing (M-TDMP) algorithm, the decoder achieves low complexity as well as fast convergence which produces high throughput of 138 Mbps working at 50 MHz. By adopting a novel scheme for early termination of iteration, the proposed decoder obtains large power efficiency. The decoder is implemented in SMIC 0.18 ¿m 1P6M CMOS technology, features a power dissipation of 179-mW operating at 50 MHz, and costs an area of 12.5 mm2.

An efficient verification and test scheme for media broadcasting demodulator

For the complex development process of media broadcasting demodulator chip, it is proposed that a low cost, high reliability verification and test scheme at system level in this paper. This scheme emphasizes the collaboration of algorithm simulation, RTL description, FPGA verification, ASIC realization and any other stages of chip development. All these stages constitute an organic, closely interconnected whole. And for the particularity of communication chip, this scheme can solve function verification and performance test, ensure the accuracy, completeness and reliability of the test and verification. Then both the development time and the cost of the product are significantly reduced. This verification and test scheme has been applied to the demodulation chip of the receiver of Chinese broadcasting standard DTMB system.

A reconfigurable power efficient correlator for channel estimation in DTMB system

This paper presents a power efficient reconfigurable correlator for DTMB channel estimation. In this design, a novel architecture based on fast Walsh transform is adopted to perform cyclic correlation. By sharing memory and reusing calculation unit, the proposed reconfigurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost. Based on SMIC 0.18 ¿m standard CMOS technology, the circuit area of presented design is about 41355 gates. The simulation results show that the proposed correlator saves 60% power consumption compared with those of the existed architectures.

design of cyclic correlator for channel estimation in DTMB system Yuan Chen Yun Chen An Pan Jun Chen Xiaoyang Zeng State Key Lab of ASIC and System, Fudan University, Shanghai 201203, China

In this paper, a cyclic-correlation based channel estimator is implemented for DTMB system. It exploits the quasi-cyclic structure of PN guard interval in DTMB system to obtain channel estimation results. Under SMIC 0.18 mum standard CMOS technology, the proposed correlator can stably work at the frequency of 60 MHz, and the circuit area is about 152 k gates. Computational simulation shows that the proposed scheme has comparable performance with FFT-based channel estimator. Implementation results demonstrate that more than 3800 clock cycles and 82% design complexity reduction can be achieved without loss in performance of rmsAMSE.

A Novel Five-Point Algorithm of Phase Noise Cancellation in DTMB

A novel five-point algorithm to remove phase noise in Chinese digital terrestrial media broadcasting system is proposed under the assumption that the bandwidth of phase noise is narrow. Simulation results demonstrate that the proposed method can provide 1–3 dB gains in AWGN and 1–4 dB in multi-path compared with those without compensation.