Dan Bao

An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13

This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row interleaving, nonzero sub-matrix reordering, sum memory quad-partition and read-write bypass, the decoder continuously scans nonzero sub-matrices two by two in the block row-wise order without any memory access conflict. Two phases are fully overlapped with each other, and the check node updating phase always takes the latest sums from the previous variable node updating phase. The sum memory stores not only the posterior sums but also the prior messages, which saves 11,520 memory bits. It only takes 48-54 clock cycles for the decoder to finish one iteration. The read-write accesses to sum memories are reduced by 24.3%-48.8%. Fabricated in the SMIC 0.13 μ m CMOS process, the decoder occupies 4.84 mm 2 with core area of 3.03 mm2, attains 847-955 Mb/s at 214 MHz and 10 iterations, and consumes 342-397 mW at 1.2 V with power efficiency of 39-46 pJ per bit per iteration.

\mu

The quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power. The architecture implements the normalized min-sum algorithm, rearranges the original two-phase message-passing flow, and adopts an efficient quantization method for the second minimum absolute values, an optimized storing scheme for the position indexes and signs, and an elaborate clock gating technique for substantive memories and registers. It is also configurable for any regular and irregular QC-LDPC codes, and can be easily tuned up to different code rates and code word lengths. The chip is fabricated in an SMIC 0.18- six-metal-layer standard CMOS technology. It attains a throughput of 104.5 Mb/s, and dissipates an average power of 486 mW at 125 MHz, and 15 decoding iterations. The core area is only 9.76 mm2. The chip has been applied into the China digital terrestrial/television multimedia broadcasting system.

m CMOS

A programmable architecture is proposed for a flexi-mode quasi-cyclic low-density parity-check code decoder. The proposed architecture has the following advantages: 1) Code rate, length, and pattern can be programmed on the fly; 2) decoding complexity is reduced by algorithm modification; 3) memory read/write operation is reduced by access optimization and hierarchical memory structure; and 4) an early stopping scheme is adopted to give power efficiency, particularly in the low-signal-to-noise-ratio region. A decoder chip is implemented in an SMIC 180-nm 1.8-V CMOS technology. Experimental results show the advantages in terms of flexibility, area, power, and error-correction performance.

An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes

In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS process with a total area of 6.3 mm2 and maximum clock frequency of 260 MHz. The estimated comsumption is 270 mW when operates at 125 MHz and 1.2V supply.

Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond

A fully-overlapped multi-mode QC-LDPC decoder architecture, adopting improved TDMP algorithm, is presented in this paper. With symmetrical four-stage pipelining, block column and row permutations, nonzero sub-matrix reordering, sum memory odd-even partition, and read-write bypass, two phases are fully overlapped and each phase scans nonzero sub-matrices one by one in block row-wise order without access conflicts to sum memories. The sum memories store not only variable node sums but also prior messages. In this case, it saves an additional FIFO of 13 440 bits. The decoder attains 248-287 Mb/s at 150 MHz and 15 iterations.

A flexible LDPC decoder architecture supporting two decoding algorithms

In this paper, we present an efficient single carrier frequency domain equalization for Advanced Television Systems Committee (ATSC) digital television receiver. The proposed scheme employs iterative cyclic prefix reconstruction (CPR) combined with block-overlapping process to reduce inter-carrier interference (ICI) component caused by the absence of cyclic prefix in multipath fading channel. In addition, trellis decoder aided iterative decision feedback frequency domain equalizer is derived to further mitigate inter-symbol interference (ISI). Finally, low-complex iterative frequency domain channel estimation is proposed to predict and track the time-varying multipath fading channel coefficients. The computer simulation results reveal that the proposed scheme has a significant performance improvement in multipath fading channel with respect to the previous time domain equalization (TDE) and frequency domain equalization (FDE).

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2 with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz.

An efficient iterative frequency domain equalization for ATSC DTV receiver

A 2304-bit flexible decoder for low-density parity-check (LDPC) codes is presented for Wireless-MAN applications. Based on modified turbo-decoding message-passing (M-TDMP) algorithm, the decoder achieves low complexity as well as fast convergence which produces high throughput of 138 Mbps working at 50 MHz. By adopting a novel scheme for early termination of iteration, the proposed decoder obtains large power efficiency. The decoder is implemented in SMIC 0.18 ¿m 1P6M CMOS technology, features a power dissipation of 179-mW operating at 50 MHz, and costs an area of 12.5 mm2.

A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS

This paper describes baseband SoC implementation of China Mobile Multimedia Broadcasting (CMMB) receiver, which integrates analog to digital (ADC), physical layer (PHY) baseband processor and medium access control (MAC) processor in single silicon wafer. MAC functions are fully implemented by firmware on an embedded 32-bit RISC-based processor. In addition, several power management techniques are utilized to reduce the power consumption of baseband SoC. The baseband SoC was successfully fabricated in 0.13μm one-poly six-metal (1P6M) CMOS process. Both analog and digital circuits are integrated on 4.8×4.8 mm2 die consuming 60mW total power dissipation under 1.2V and 3.3V supplies. The experiment results reveal the proposed baseband SoC has excellent performance under the multipath channels.

A 179-mW 2304-bit flexible LDPC decoder for Wireless-MAN applications

An energy-efficient programmable LDPC decoder is proposed for WiMax and Wi-Fi applications. The proposed decoder is designed with overlapped processing units, flexible message passing network and medium-grain partitioned memories to achieve flexibility, area reduction, and energy efficiency. The decoder can be programmed by host processor with several special-purpose micro-instructions. Thus, various operation modes can be reconfigured. Fabricated in SMIC 0.13μm 1P8M CMOS process, the chip occupies 4.32 mm2 with core area 2.97 mm2, and consumes 170mW with a throughput of 302Mb/s when operating at 145MHz and 1.2V.