An Tong

Strain rate effect and Johnson-Cook models of lead-free solder alloys

Drop/impact causes high strain rate deformation in solder joints of microelectronics package. It is important to understand mechanical behavior of solder joints under high strain rate for reliability design of products. In this paper mechanical behaviors of two lead-free solder alloys, Sn3.5Ag and Sn3.0Ag0.5Cu, were investigated by quasi-static tests and the split Hopkinson tension/pressure bar testing technique under high strain rate (600~2200s-1). The experimental results show that the two materials are sensitive to strain rate and their dynamic flow stresses are much greater than their static flow stresses. The higher the strain rate, the greater their tensile strength but less their fracture strains. Based on the experimental data, constitutive models in the Johnson-Cook form for the two lead-free alloys were derived. The models were then used to simulate the testing process by incorporating it into ABAQUS. The good agreement between the numerical simulations and the experiments indicates that the presented Johnson-Cook models are suitable and reliable to describe dynamic behavior of the two solder alloys under high strain rates. Finally, the proposed constitutive models were used to compute peeling stress and plastic strain of solder joints under drop/impact loadings, and the results were compared with that by linear elastic model and tri-linear elastic-plastic model to show the necessity of using a strain rate dependent material model in simulation of drop/impact of solder joints.

Effect of Electroplating Parameter on the TSV-Cu Protrusion During Annealing

Four level sets of current density and additive concentration are used to electroplate copper into the through silicon via to prepare four sets of test samples. Each set of samples are annealed at 425°C for 30min. The Cu-Si interface of the TSV structure and the copper microstructure are observed before and after annealing, and the copper protrusion is measured after annealing. Effects of the electroplating parameter on protrusion of copper filled in through silicon via (TSV-Cu) after annealing are investigated experimentally. The results show that, higher electroplating current density and higher additive concentration can help to fabricated finer grained TSV-Cu. The TSV-Cu with finer grain protrudes less after the annealing process. With the protrusion occurs, the Cu-Si interface fracture is observed for all the samples.

An equivalent model of TSV silicon interposer

The silicon layer containing through silicon vias (TSVs) is considered as anisotropic fiber reinforced composite layer with different longitudinal and transversal properties. An analytical approach is presented to estimate the effective Youngs modulus, Poissons ratio and coefficient of thermal expansion (CTE) for composite layer. It shows that the TSVs have no significant influence on the deflection of silicon layer, and the model ignoring TSVs is capable to predict enough accurate deflection of silicon layer.

A constitutive model for lead-free solders considering the damage effect at high strain rates

The rate-dependent Johnson-Cook material model can predict the stresses and strains of lead-free solder when the strain rate is relatively low (600 s−1). At higher strain rates (1200 s−1 or above), the stress-strain curves predicted by Johnson-Cook model do not agree well with the experimental results when the strain exceeds a threshold value. In this paper, the damage effect is considered into the impact process of lead-free solder specimens.

Morphology and nanoindentation properties of intermetallic compounds in solder joints

The growth of intermetallic compounds (IMC) at the Sn3.0Ag0.5Cu/Cu interface is investigated under aging temperature of 150 °C and aging time of 100, 300 and 500 hours. The relationship between the thickness of the IMC and aging time is fitted out, and the growth law of the IMC at Sn3.0Ag0.5Cu/Cu interface under isothermal aging condition is obtained. Mechanical properties of the Cu<inf>6</inf>Sn<inf>5</inf> and Cu<inf>3</inf>Sn are obtained by a G200 nanoindentation tester. It indicates that with the Cu<inf>6</inf>Sn<inf>5</inf> thickness increases, its Youngs modulus and hardness have no change. The Youngs modulus of Cu<inf>3</inf>Sn is greater than that of Cu<inf>6</inf>Sn<inf>5</inf>, but the hardness of Cu<inf>3</inf>Sn is lower than that of Cu<inf>6</inf>Sn<inf>5</inf>. The nanoindentation experiments of the Sn3.0Ag0.5Cu/Cu interfacial zone show that the hardness of Cu, Cu<inf>3</inf>Sn, Cu<inf>6</inf>Sn<inf>5</inf> and Sn3.0Ag0.5Cu has an order in magnitude of Cu<inf>6</inf>Sn<inf>5</inf> > Cu<inf>3</inf>Sn > Cu > Sn3.0Ag0.5Cu.

Finite element based DOE methodology for thermal fatigue reliability design of multi-row QFN packages

A DOE (Design of Experiment) methodology based on finite element analysis is presented to investigate thermal fatigue reliability of multi-row QFN packages. In this method, the influences of material properties, structural geometries and temperature cycling profiles on thermal fatigue reliability are evaluated, a L27(38) orthogonal array is built based on Taguchi method to figure out optimized factor combination design for promoting thermal fatigue reliability. Anand constitutive model is adopted to describe the viscoplastic behavior of lead-free solder Sn3.0Ag0.5Cu. The stress and strain in solder joints under temperature cycling are studied by 3D finite element model. The modified Coffin-Manson model is employed to predict the fatigue life of solder joints. Results indicate that CTE of PCB board, the height of solder joint and CTE of epoxy molding compound have critical influence on thermal fatigue life of solder joints. The fatigue life of multi-row QFN package with original design is 767 cycles, which can be substantially improved by 5.43 times to 4165 cycles after optimized factor combination design.

Interfacial stress in Through Silicon Vias

Through Silicon Via (TSV) has emerged as a good solution to provide high density interconnections in three-dimensional packaging interconnect technologies. However, the thermal-mechanical reliability is a big issue. When the TSV is subjected to thermal load, large stress and strain would be created at the interface of the materials because of the great mismatch of CTE. In this paper, an axi-symmetric single TSV model with RDL layer is taken into consideration. A static temperature difference of Δt=165°C is carried out to simulate the thermal stress, effects of via size and the interposer height on the stress are investigated. Effect of SiO2 layer on Cu and Si is also analyzed. In addition, the shear stress of interface, under thermal cycles from -40°C to 125°C, is computed. In the simulation model, the kinematic hardening material model of Cu is used.

Dynamic bending tests and numerical simulation of board level electronic package

4-point dynamic bending tests of board level electronic packages were carried out in order to investigate the reliability of solder joints. A high speed camera and the digital image correlation method were used to measure the deflection of the PCB board. A finite element model to simulate the test was built up and was validated by the test data. A parameter study was subsequently implemented. The results show that at certain value of PCB stiffness the peeling stress reaches its peak. The package installation angel has significant effect on the peeling stress of the solder joints.

Analysis the interface delamination of Cu and EMC adhesive material in the cutting process of electronic chip based on cohesive zone modeling

In this paper, cohesive zone modeling (CZM) was adopted to simulate the distribution of temperature & stress field and the interface damage on the Cu/EMC double adhesive material electronic packaging. The following phenomena were found: A sharp rise of the EMC temperature appeared at cut portion field when the cutting began, while it had little effect on copperplate. Stress concentration existed at the cutting surface boundary, and the maximum value occurred at the top of the copper plate which had exceed the yield and tensile strength of the viscoelastic copper, this will be prone to drag and generate burr on the copper surface. Contact surface damage occurred mainly in first time step, the first site of injury occurred in the medial side of the cutting surface. The interfacial tension stress was smaller than the maximum normal stress set up by CZM, while the interface tangential stress was greater than the maximum tangential contact stress that the material can bear, which would cause damage to the bonding interface. Compared with normal strain energy release rate due to separation in normal direction (mode I debonding), shear strain energy release rate due to separation in tangential direction(mode II debonding) was larger, but it did not reach the critical strain energy release rate in the shear directions. The contact interface was not completely cracked and cracking trend was mainly mode II crack in this case.

Numerical simulation of the intermetallic compound cracking in solder joint

The microcracking behavior of the IMC layer is investigated numerically, and the effect of the thickness of the IMC layer on the overall response and failure mode of the solder joint is studied using qualitative numerical simulations. The results show that the thicker IMC layer results in lower overall strength. When the IMC layer is thin, the microcracks tend to start at the valley of the rough solder/IMC interface and propagate across the root of the protruding Cu6Sn5 grains; when the IMC layer is thick, the microcracks tend to occur within the IMC layer. These predictions agree well with experimental observations.