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Featured researches published by Liu Chengyan.


international conference on electronic packaging technology | 2013

Non-destructive testing for defects in electronic package based on Infrared Thermography

Liu Chengyan; Qin Fei; Ban Zhaowei

Defects such as interfacial delaminations degrade the yield rate and reliability of the device. Its important to find and evaluate these defects on time. Infrared Thermography is proved to be a valuable tool for non-destructive testing of materials. In this paper the relationship between the thermal characteristics of the sample surface and the defect feature parameters is investigated using Infrared Thermography; while an approach to quantitatively evaluate the defect is proposed.


international conference on electronic packaging technology | 2011

Morphology and nanoindentation properties of intermetallic compounds in solder joints

Zhong Weixu; Qin Fei; An Tong; Liu Chengyan

The growth of intermetallic compounds (IMC) at the Sn3.0Ag0.5Cu/Cu interface is investigated under aging temperature of 150 °C and aging time of 100, 300 and 500 hours. The relationship between the thickness of the IMC and aging time is fitted out, and the growth law of the IMC at Sn3.0Ag0.5Cu/Cu interface under isothermal aging condition is obtained. Mechanical properties of the Cu<inf>6</inf>Sn<inf>5</inf> and Cu<inf>3</inf>Sn are obtained by a G200 nanoindentation tester. It indicates that with the Cu<inf>6</inf>Sn<inf>5</inf> thickness increases, its Youngs modulus and hardness have no change. The Youngs modulus of Cu<inf>3</inf>Sn is greater than that of Cu<inf>6</inf>Sn<inf>5</inf>, but the hardness of Cu<inf>3</inf>Sn is lower than that of Cu<inf>6</inf>Sn<inf>5</inf>. The nanoindentation experiments of the Sn3.0Ag0.5Cu/Cu interfacial zone show that the hardness of Cu, Cu<inf>3</inf>Sn, Cu<inf>6</inf>Sn<inf>5</inf> and Sn3.0Ag0.5Cu has an order in magnitude of Cu<inf>6</inf>Sn<inf>5</inf> > Cu<inf>3</inf>Sn > Cu > Sn3.0Ag0.5Cu.


international conference on electronic packaging technology | 2012

Interfacial stress in Through Silicon Vias

Li Wei; Qin Fei; An Tong; Wu Wei; Liu Chengyan; Wan Lixi; Yu Daquan; Wang Jun

Through Silicon Via (TSV) has emerged as a good solution to provide high density interconnections in three-dimensional packaging interconnect technologies. However, the thermal-mechanical reliability is a big issue. When the TSV is subjected to thermal load, large stress and strain would be created at the interface of the materials because of the great mismatch of CTE. In this paper, an axi-symmetric single TSV model with RDL layer is taken into consideration. A static temperature difference of Δt=165°C is carried out to simulate the thermal stress, effects of via size and the interposer height on the stress are investigated. Effect of SiO2 layer on Cu and Si is also analyzed. In addition, the shear stress of interface, under thermal cycles from -40°C to 125°C, is computed. In the simulation model, the kinematic hardening material model of Cu is used.


international conference on electronic packaging technology | 2011

Influence of interfacial delamination on temperature distribution of QFN packages

Ban Zhaowei; Qin Fei; An Tong; Xia Guofeng; Liu Chengyan

Infrared thermography has become increasingly important for non-destructive testing to detect internal defections, involving delaminations, cracks and voids. In this paper, the principle of infrared thermography is presented briefly. And a finite element approach is proposed to simulate the process of infrared thermography nondestructive testing about QFN packages. By changing with the length and the thickness of the delamination and the size of uniform surface heat flux, the surface thermal characteristics of a QFN are analyzed. The simulation results can provide basis and reference for the following work to detect defects in packages by infrared thermography method.


Archive | 2013

Semiconductor PiP (package in package) system structure and manufacturing method thereof

Qin Fei; Xia Guofeng; An Tong; Liu Chengyan; Wu Wei; Zhu Wenhui


Archive | 2013

Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method

Qin Fei; Xia Guofeng; An Tong; Wu Wei; Liu Chengyan; Zhu Wenhui


Archive | 2013

QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof

Qin Fei; Xia Guofeng; An Tong; Wu Wei; Liu Chengyan; Zhu Wenhui


Archive | 2014

Method for testing processing residual stress of 'through-silicon via'-Cu structure

Qin Fei; Wu Wei; An Tong; Xia Guofeng; Liu Chengyan; Yu Daquan; Wan Lixi


Archive | 2013

Wafer level chip size package and manufacturing method thereof

Qin Fei; Wu Wei; An Tong; Liu Chengyan; Chen Si; Xia Guofeng; Zhu Wenhui


Archive | 2013

Manufacturing method for rewiring quad flat no-lead (QFN) packaging component

Qin Fei; Xia Guofeng; An Tong; Liu Chengyan; Wu Wei; Zhu Wenhui

Collaboration


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Qin Fei

Beijing University of Technology

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An Tong

Beijing University of Technology

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Wu Wei

Beijing University of Technology

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Xia Guofeng

Beijing University of Technology

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Zhu Wenhui

Beijing University of Technology

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Wang Xiaoliang

Beijing University of Technology

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Chen Si

Beijing University of Technology

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Wan Lixi

Chinese Academy of Sciences

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Yu Daquan

Dalian University of Technology

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Ban Zhaowei

Beijing University of Technology

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