An Xia

Effects of heavy ion irradiation on ultra-deep-submicron partially-depleted SOI devices

The effects of the physical damages induced by heavy ion irradiation on the performance of partially-depleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance, and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design.

Impact of the displacement damage in channel and source/drain regions on the DC characteristics degradation in deep-submicron MOSFETs after heavy ion irradiation

This paper mainly reports the permanent impact of displacement damage induced by heavy-ion strikes on the deep-submicron MOSFETs. Upon the heavy ion track through the device, it can lead to displacement damage, including the vacancies and the interstitials. As the featured size of device scales down, the damage can change the dopant distribution in the channel and source/drain regions through the generation of radiation-induced defects and thus have significant impacts on their electrical characteristics. The measured results show that the radiation-induced damage can cause DC characteristics degradations including the threshold voltage, subthreshold swing, saturation drain current, transconductance, etc. The radiation-induced displacement damage may become the dominant issue while it was the secondary concern for the traditional devices after the heavy ion irradiation. The samples are also irradiated by Co-60 gamma ray for comparison with the heavy ion irradiation results. Corresponding explanations and analysis are discussed.

Fabricating GeO2 passivation layer by N2O plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N2O plasma oxidation at 300 °C. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N2O plasma passivation is about ~ 3 × 1011 cm−2eV−1. With GeO2 passivation, the hysteresis of metal—oxide—semiconductor (MOS) capacitor with Al2O3 serving as gate dielectric is reduced to ~ 50 mV, compared with ~ 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.

Schottky Barrier Height Modulation of Nickel Germanide Schottky Diodes by the Germanidation-Induced Dopant Segregation Technique

Modulation of Schottky barrier height (SBH) is successfully demonstrated by a germanidation-induced dopant segregation technique. The barrier height of NiGe/Ge Schottky diodes is modulated by 0.06−0.15eV depending on annealing temperature. The results show the change of SBH is not attributed to the phase change of nickel germanides but to dopant segregation at the interface of germanides/germanium which causes the upward conduction energy band. In addition, we first observe a Raman peak at about 217 cm−1 corresponding to NiGe, which has not been reported till now. The surface morphology of nickel germanides can be improved by BF2 implantation before germanidation. The results may provide guidelines for the design of Schottky source/drain germanium-based devices.

The modulation of Schottky barrier height of NiSi/n-Si Schottky diodes by silicide as diffusion source technique

This paper reports that the Schottky barrier height modulation of NiSi/n-Si is experimentally investigated by adopting a novel silicide-as-diffusion-source technique, which avoids the damage to the NiSi/Si interface induced from the conventional dopant segregation method. In addition, the impact of post-BF2 implantation after silicidation on the surface morphology of Ni silicides is also illustrated. The thermal stability of Ni silicides can be improved by silicide-as-diffusion-source technique. Besides, the electron Schottky barrier height is successfully modulated by 0.11 eV at a boron dose of 1015 cm−2 in comparison with the non-implanted samples. The change of barrier height is not attributed to the phase change of silicide films but due to the boron pile-up at the interface of NiSi and Si substrate which causes the upward bending of conducting band. The results demonstrate the feasibility of novel silicide-as-diffusion-source technique for the fabrication of Schottky source/drain Si MOS devices.

Line-edge roughness induced single event transient variation in SOI FinFETs

The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration ( V gs =0, V ds = V dd ) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interfacial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness (EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.

Heavy ion induced electrical property degradation in sub-100 nm bulk silicon MOS devices

The radiation response of 90 nm bulk silicon MOS devices after heavy ion irradiation is experimentally investigated. Due to the random strike of the incident particle, different degradation behaviors of bulk silicon MOS devices are observed. The drain current and maximum transconductance degrade as a result of the displacement damage in the channel induced by heavy ion strike. The off-state leakage current degradation and threshold voltage shift are also observed after heavy ion irradiation. The results suggest that the radiation induced damage of sub-100 nm MOS devices caused by heavy ion irradiation should be paid attention.

Research on HCI lifetime prediction methodology based on self-heating removal for SOI NMOSFETs

Self-heating effect (SHE) is one of the key concerns for the reliability issues of SOI MOSFETs. The unavoidable SHE during HCI test may underestimate the devices performance and lead to the inaccurate lifetime prediction. In this paper, a new method is proposed to accurately predict the lifetime of 0.18 μm PD-SOI NMOS device based on DC HCI stress. The temperature increase (Tsh) caused by SHE is quantitatively extracted by gate resistance measurement. Then, the degradation part due to SHE is removed to accurately extrapolate lifetime of PD-SOI NMOSFET device using substrate/drain current ratio model. As a result, the extrapolated lifetime of 0.18 μm SOI NMOS illustrates a significant difference by 63.5% whether considering removal of SHE or not, indicating that the impact of SHE on the reliability issue of SOI device can not be ignored, otherwise leading to the inaccurate lifetime prediction.

Experimental clarification of orientation dependence of germanium PMOSFETs with Al2O3/GeOx/Ge gate stack

An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal—oxide—semiconductor field-effect transistors (PMOSFETs). By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is (110)>(111) ~ (100), and the best channel direction is (110)/[110]. Moreover, the (110) device performance was found to be easily degraded as the channel direction got off from the [110] orientation, while (100) and (111) devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.