Huang Ru

A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.

Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation

In this paper, a method to fabricate Silicon-on-Nothing (SON) MOSFETs using H+ and He+ co-implantation is presented. The technique is compatible with conventional CMOS technology and its feasibility has been experimentally demonstrated. SON MOSFETs with 50nm gate length have been fabricated. Compared with the corresponding bulk MOSFETs, the SON MOSFETs show higher on current, reduced leakage current and lower subthreshold slope.

Radio-frequency transistors from millimeter-scale graphene domains

Graphene is a new promising candidate for application in radio-frequency (RF) electronics due to its excellent electronic properties such as ultrahigh carrier mobility, large threshold current density, and high saturation velocity. Recently, much progress has been made in the graphene-based RF field-effect transistors (RF-FETs). Here we present for the first time the high-performance top-gated RF transistors using millimeter-scale single graphene domain on a SiO2/Si substrate through a conventional microfabrication process. A maximum cut-off frequency of 178 GHz and a peak maximum oscillation frequency of 35 GHz are achieved in the graphene-domain-based FET with a gate length of 50 nm and 150 nm, respectively. This work shows that the millimeter-scale single graphene domain has great potential applications in RF devices and circuits.

Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate (DG) and gate-all-around (GAA) MOSFETs have been investigated by three-dimensional (3D) and two-dimensional (2D) simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL (drain induced barrier lowering) effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.

The simulation analysis of cross-talk behavior in SOI mixed-mode integrated circuits

With the two-dimensional (2D) TMA medici simulator, the systematic analysis of cross-talk behavior is presented for different SOI mixed-mode integrated circuits such as PD (partially-depleted), FD (fully-depleted) and BC (body-contacted) structures. It is found that the substrate-grounded SOI structure can lower the noise coupling to a large extent compared to the substrate-floating one. Besides, the efficiency of different strategies for reducing cross-talk such as trench isolation, capacitive guard ring and distance separating is also investigated. The results are very important for evaluating cross-talk effects in low-noise coupling SOI mixed-mode ICs.

Effects of heavy ion irradiation on ultra-deep-submicron partially-depleted SOI devices

The effects of the physical damages induced by heavy ion irradiation on the performance of partially-depleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance, and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design.

Microelectronics technologies in renewable energy internet

Renewable energy internet proposes five requirements for electronic system: efficiency, safety, reliability, convenience, extensiveness. In order to achieve the above requirements, renewable energy internet demands a multi-disciplinary, multi-faceted, multi-level innovation. Microelectronics technology will permeate all levels of renewable energy internet, performing as one of the important supporting technologies of renewable energy internet. This paper will focus on solid state transformers, distributed energy storage technology, information acquisition chip technology, communications chip technology, describing the special requirements, technical challenges, trend of development of microelectronics in renewable energy internet.

Vertical assembly of carbon nanotubes for via interconnects

The via interconnects are key components in ultra-large scale integrated circuits (ULSI). This paper deals with a new method to create single-walled carbon nanotubes (SWNTs) via interconnects using alternating dielectrophoresis (DEP). Carbon nanotubes are vertically assembled in the microscale via-holes successfully at room temperature under ambient condition. The electrical evaluation of the SWNT vias reveals that our DEP assembly technique is highly reliable and the success rate of assembly can be as high as 90%. We also propose and test possible approaches to reducing the contact resistance between CNT vias and metal electrodes.

Impact of the displacement damage in channel and source/drain regions on the DC characteristics degradation in deep-submicron MOSFETs after heavy ion irradiation

This paper mainly reports the permanent impact of displacement damage induced by heavy-ion strikes on the deep-submicron MOSFETs. Upon the heavy ion track through the device, it can lead to displacement damage, including the vacancies and the interstitials. As the featured size of device scales down, the damage can change the dopant distribution in the channel and source/drain regions through the generation of radiation-induced defects and thus have significant impacts on their electrical characteristics. The measured results show that the radiation-induced damage can cause DC characteristics degradations including the threshold voltage, subthreshold swing, saturation drain current, transconductance, etc. The radiation-induced displacement damage may become the dominant issue while it was the secondary concern for the traditional devices after the heavy ion irradiation. The samples are also irradiated by Co-60 gamma ray for comparison with the heavy ion irradiation results. Corresponding explanations and analysis are discussed.

Fabricating GeO2 passivation layer by N2O plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N2O plasma oxidation at 300 °C. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N2O plasma passivation is about ~ 3 × 1011 cm−2eV−1. With GeO2 passivation, the hysteresis of metal—oxide—semiconductor (MOS) capacitor with Al2O3 serving as gate dielectric is reduced to ~ 50 mV, compared with ~ 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.