Anand D. Darji

Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

In this brief, an efficient dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform is presented. This proposed novel algorithm is based on a flipping technique to implement a modular and hardware-efficient architecture with a very simple control path. In the proposed algorithm, the serial operation of the lifting data flow is optimized using parallel computations of independent paths in advance with pipeline operation to minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency. The proposed architecture is repeatable and only uses five transposition registers. The architecture can be folded to reduce the data path to only six multipliers and eight adders without affecting the critical path. The architecture implemented on a field-programmable gate-array target indicates better hardware efficiency.

Design and implementation of real-time image watermarking

The digital watermarking is a multimedia technology for information hiding which provides the authentication and copyright protection. The digital images are easily exchanged through internet and threaten to some malicious attacks. Wavelet based frequency domain watermarking provides the robustness against different attacks. Bit plane slicing scheme of spatial domain watermarking provides lesser computational complexity suitable for real time implementation. We combine advantages of the both the domains for the proposed algorithm. We have developed algorithm for robust and invisible application where we used non blind detection scheme. This approach is also implemented on FPGA. Several software implementations of the watermarking algorithms are available, but very few attempts have been made for hardware implementations. Software based watermarking schemes are more prone to offline attacks due to the delay between image captured and embedding the watermark. Hardware based watermarking provides real time embedding process where watermark is embedded at the same time when image is captured. This is very much useful in applications like real-time broad casting, video authentication and secure camera system for courtroom evidence. The goal of hardware implementation is to achieve low-power, high-performance, real-time, reliable and secure watermarking systems using FPGA.

Efficient Dual Domain Watermarking Scheme for Secure Images

Day to day growth of multimedia technology draws great attention for security. Digital images can be easily altered with software. This problems demand copyright protection and ownership verification. Digital watermarking is proposed as one of the ways to accomplish this, in which Digital watermarks are generally embedded into digital images in a manner that make the watermark invisible to a human observer as such watermarks do not cause degradation in the visual quality, or in the usefulness of the images. Digital watermarking is a technique to insert owner’s identity into images for authentication. Digital watermarking has emerged as a new area of research for the Intellectual Property (IP) protection of images. Spatial domain watermarking has advantage of less computational cost. Frequency domain watermarking provides more robustness. The proposed algorithm has been developed to take advantage of both spatial as well as frequency domain properties.

An area efficient and low power implementation of 2048 point FFT/IFFT processor for mobile WiMAX

A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for IEEE standard WiMAX 802.16e. The FFT/IFFT processor is synthesized using UMC 0.18 μm CMOS technology and saves 33% area compared to a conventional implementation approach using radix-2 algorithm without sacrificing system throughput. Proposed Architecture also provides concept of local ROM module, optimized complex multiplier and variable length support from 128-2048 point for FFT/IFFT. Its core size is 2.13 mm × 2.13 mm with 51.25 μs execution time. Its latency is 2050 clock cycle with maximum clock frequency 40 MHz. Start up time for the chip is N/2 clock cycle where N is the length of FFT/IFFT. 16 bit word length with fixed point precision is used for entire implementation. The processor consumes 55.64mW at 40 MHz, 29.13 mW at 20 MHz for length 2048-point and can be Efficiently used for IEEE 802.16e WiMAX standard.

High-performance multiplierless DCT architecture for HEVC

There are numerous video compression format for storage or transmission of digital video content. High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 Advanced Video Coding (AVC), that was jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265. In this paper, we propose an efficient architecture for the computation of 4, 8, 16 and 32 point DCT used in HEVC standard. The architecture uses the Canonical Signed Digit (CSD) representation and Common Sub-expression Elimination (CSE) technique to perform the multiplication with shift-add operation. The proposed architecture requires less number of adders and shifters and gives almost double throughput as compared to the previous work. Number of Logic Elements (LEs) required for the implementation is reduce by almost 36% without compromising throughput. The hardware cost reduces due to the reduction in arithmetic operation.

Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform

In this study, the authors present a multiplier-less, high-speed and low-power pipeline architecture with novel dual Z-scanning technique for lifting-based two-dimensional (2D) discrete wavelet transform (DWT). The proposed architecture is composed of pipeline one-dimensional row, column processors and five transposing registers. Moreover, it uses 4N temporal line buffers to process 2D DWT of image with N × N resolution. Multipliers are designed with shift-and-add logic to reduce the critical path to one adder. Dual Z-scanning method is employed to reduce the transposition buffers and latency. The proposed architecture is superior to the existed architectures in speed, power and hardware utilisation for similar throughput specification. Register transfer logic (RTL) of the proposed design is described using VHDL and synthesised using Xilinx ISE 10.1. The proposed architecture operates at a frequency of 353.107 MHz, when synthesised for Xilinx Virtex-IV series field programmable gate array. Frame processing rate of 340 frames/second for full high-definition video can be achieved at this frequency of operation. RTL of the proposed design is synthesised using UMC 180 nm technology complementary metal-oxide semiconductor (CMOS) standard cell library for application specific integrated circuit (ASIC) implementation. ASIC synthesis of 2D DWT core uses 20 358 logic gates and consumes only 20.83 mW power at 100 MHz frequency.

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

In this paper, three hardware efficient architectures to perform multi-level 2-D discrete wavelet transform (DWT) using lifting (5, 3) and (9, 7) filters are presented. They are classified as folded multi-level architecture (FMA), pipelined multi-level architecture (PMA), and recursive multi-level architecture (RMA). Efficient FMA is proposed using dual-input Z-scan block (B1) with 100% hardware utilization efficiency (HUE). Modular PMA is proposed with the help of block (B1) and dual-input raster scan block (B2) with 60% to 75% HUE. Block B1 and B2 are micro-pipelined to achieve critical path as single adder and single multiplier for lifting (5, 3) and (9, 7) filters, respectively. The clock gating technique is used in PMA to save power and area. Hardware-efficient RMA is proposed with the help of block (B1) and single-input recursive block (B3). Block (B3) uses only single processing element to compute both predict and update; thus, 50% multipliers and adders are saved. Dual-input per clock cycle minimizes total frame computing cycles, latency, and on-chip line buffers. PMA for five-level 2-D wavelet decomposition is synthesized using Xilinx ISE 10.1 for Virtex-5 XC5VLX110T field-programmable gate array (FPGA) target device (Xilinx, Inc., San Jose, CA, USA). The proposed PMA is very much efficient in terms of operating frequency due to pipelining. Moreover, this approach reduces and totals computing cycles significantly as compared to the existing multi-level architectures. RMA for three-level 2-D wavelet decomposition is synthesized using Xilinx ISE 10.1 for Virtex-4 VFX100 FPGA target device.

VLSI Architecture of DWT Based Watermark Encoder for Secure Still Digital Camera Design

Digital watermarking is the technique used to embed author’s credentials, logo or some other information into digital images which can be used in authentications for courtroom evidence, copyright claims and other applications. The objective of this work is to develop a feasible and invisible watermark embedding hardware for the secure digital cameras using LeGall 5/3 (Discrete Wavelet Transform) DWT. Bind watermarking tecnique is proposed here. The proposed architecture considers constraints of digital camera such as area, speed, power, robustness and invisibility. The algorithm is evaluated under the attacks like JPEG (Joint Photographic Experts Group) compression, noise, scaling and rotation to verify robustness and invisibility properties. Watermarking processor is described using Verilog HDL and synthesized using 0.18 µm technology UMC standard cell library for VLSI implementation.

Optimized drivers for PS/2 and VGA using HDL

FPGA is increasingly popular as it has reliable prototyping, low cost and high speed. Input/output interfacing is inevitable for any system. So, the necessary signals for VGA and PS/2 interface are generated using HDL. The design is synthesized and implemented in Xilinx Virtex-II Pro. The mapped signals in FPGA Board are optimized to minimize resource utilization. The entire design is implemented in hardware with a VGA monitor and a PS/2 keyboard.

Memory efficient VLSI architecture for lifting-based DWT

In this paper, a new lifting-based DWT architecture for CDF 9/7 filter is proposed which has lowest temporal memory among the existing architectures. This is achieved with a modified overlapped-scanning method and recalculation of one intermediate DWT coefficient. The proposed architecture requires only 2N temporal memory to process N × N sized image. The architecture has a critical path of one multiplier delay and demonstrates 100% hardware utilization efficiency.