Arun N. Chandorkar

Optically Controlled Frequency-Reconfigurable Microstrip Antenna With Low Photoconductivity

In this letter, novel designs for optically switching the resonant frequency of a microstrip patch antenna via photoconductive switches are proposed, and design considerations for maximizing frequency switching ratio with finite photo-conductance are investigated. Furthermore, a configuration to switch the resonant frequency with low switch conductance is proposed for cheap and easy fabrication of a frequency-reconfigurable antenna that can be operated with low optical power. Experimental verification of the low-power configuration is presented.

Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

In this brief, an efficient dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform is presented. This proposed novel algorithm is based on a flipping technique to implement a modular and hardware-efficient architecture with a very simple control path. In the proposed algorithm, the serial operation of the lifting data flow is optimized using parallel computations of independent paths in advance with pipeline operation to minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency. The proposed architecture is repeatable and only uses five transposition registers. The architecture can be folded to reduce the data path to only six multipliers and eight adders without affecting the critical path. The architecture implemented on a field-programmable gate-array target indicates better hardware efficiency.

On-chip Test and Repair of Memories for Static and Dynamic Faults

In addition to static faults, dynamic faults are increasingly important for high density embedded memories due to aggressive design rules and shrinking feature sizes. Not only is the test of these faults important, their repair is important too for devices where the yield loss due to memory fails is significant. Dynamic faults can impact one or more memory cells. In the case of the latter, it is also important to diagnose the cell causing the fault, and hence to be repaired. This paper describes an on-chip test and repair solution for static and dynamic faults in random access memories. The main contributions of this paper are three fold: (i) development of new algorithms for detection of static and dynamic faults, and for identification of faulty aggressor cells, (ii) extension of fault syndromes for diagnosis and location of aggressor cells, and (iii) development of an on-chip test, analysis and repair solution implementing these algorithms. It is shown how the proposed fault detection algorithms and redundancy analysis schemes are superior to existing ones for analysis time, hardware overhead, fault coverage and aggressor location capability

Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method

This paper studies various double-gate (DG) FinFET structures optimized for better ¿off state¿ and ¿on state¿ performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20 nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on Ion of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman design of experiments (PB-DOE), for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET device¿s electrical performance.

Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories

Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and a limited coupling between them. The algorithms used in these tests have been successively augmented to consider stronger coupling conditions. Built-in self-test (BIST) solutions for testing memories today incorporate hardware for test pattern generation and application for a variety of these algorithms. This paper presents a BIST implementation for detection of neighbourhood pattern sensitive faults (NPSFs) in random access memories (RAMs). These faults are of different classes and types. More specifically, active, passive and static faults for distance 1 and 2 neighbourhoods, of types 1 and 2, are considered. It is shown how the proposed address generation and test pattern generation schemes can be made scaleable for the given fault type under consideration.

Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform

In this study, the authors present a multiplier-less, high-speed and low-power pipeline architecture with novel dual Z-scanning technique for lifting-based two-dimensional (2D) discrete wavelet transform (DWT). The proposed architecture is composed of pipeline one-dimensional row, column processors and five transposing registers. Moreover, it uses 4N temporal line buffers to process 2D DWT of image with N × N resolution. Multipliers are designed with shift-and-add logic to reduce the critical path to one adder. Dual Z-scanning method is employed to reduce the transposition buffers and latency. The proposed architecture is superior to the existed architectures in speed, power and hardware utilisation for similar throughput specification. Register transfer logic (RTL) of the proposed design is described using VHDL and synthesised using Xilinx ISE 10.1. The proposed architecture operates at a frequency of 353.107 MHz, when synthesised for Xilinx Virtex-IV series field programmable gate array. Frame processing rate of 340 frames/second for full high-definition video can be achieved at this frequency of operation. RTL of the proposed design is synthesised using UMC 180 nm technology complementary metal-oxide semiconductor (CMOS) standard cell library for application specific integrated circuit (ASIC) implementation. ASIC synthesis of 2D DWT core uses 20 358 logic gates and consumes only 20.83 mW power at 100 MHz frequency.

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

In this paper, three hardware efficient architectures to perform multi-level 2-D discrete wavelet transform (DWT) using lifting (5, 3) and (9, 7) filters are presented. They are classified as folded multi-level architecture (FMA), pipelined multi-level architecture (PMA), and recursive multi-level architecture (RMA). Efficient FMA is proposed using dual-input Z-scan block (B1) with 100% hardware utilization efficiency (HUE). Modular PMA is proposed with the help of block (B1) and dual-input raster scan block (B2) with 60% to 75% HUE. Block B1 and B2 are micro-pipelined to achieve critical path as single adder and single multiplier for lifting (5, 3) and (9, 7) filters, respectively. The clock gating technique is used in PMA to save power and area. Hardware-efficient RMA is proposed with the help of block (B1) and single-input recursive block (B3). Block (B3) uses only single processing element to compute both predict and update; thus, 50% multipliers and adders are saved. Dual-input per clock cycle minimizes total frame computing cycles, latency, and on-chip line buffers. PMA for five-level 2-D wavelet decomposition is synthesized using Xilinx ISE 10.1 for Virtex-5 XC5VLX110T field-programmable gate array (FPGA) target device (Xilinx, Inc., San Jose, CA, USA). The proposed PMA is very much efficient in terms of operating frequency due to pipelining. Moreover, this approach reduces and totals computing cycles significantly as compared to the existing multi-level architectures. RMA for three-level 2-D wavelet decomposition is synthesized using Xilinx ISE 10.1 for Virtex-4 VFX100 FPGA target device.

VLSI Architecture of DWT Based Watermark Encoder for Secure Still Digital Camera Design

Digital watermarking is the technique used to embed author’s credentials, logo or some other information into digital images which can be used in authentications for courtroom evidence, copyright claims and other applications. The objective of this work is to develop a feasible and invisible watermark embedding hardware for the secure digital cameras using LeGall 5/3 (Discrete Wavelet Transform) DWT. Bind watermarking tecnique is proposed here. The proposed architecture considers constraints of digital camera such as area, speed, power, robustness and invisibility. The algorithm is evaluated under the attacks like JPEG (Joint Photographic Experts Group) compression, noise, scaling and rotation to verify robustness and invisibility properties. Watermarking processor is described using Verilog HDL and synthesized using 0.18 µm technology UMC standard cell library for VLSI implementation.

Response Surface Methodology for statistical characterization of nano CMOS devices and circuits

The accurate prediction of the impact of process variations on circuit performance is very crucial in deciding the parametric yield of integrated circuits. This paper presents the simulation methodology for studying the impact of process variations on device and circuit performance in nanometer regime. In this paper, an empirical model for power and delay of 45 nm node CMOS inverter is build using the well-known response surface methodology. This work also compares the suitability of different response design in terms of model accuracy.

Design of amplifier with rail-to-rail CMR with 1 V power supply

The continuous reduction of power supply voltage for VLSI circuits put forward new challenges for analog designers. In this paper we present a low-voltage CMOS amplifier with rail-to-rail input common-mode range. The amplifier was designed with 1 V supply voltage in standard digital technology. Alternative methods were applied for obtaining high ICMR, good CMRR and output swing at such low supply voltage. A bandgap reference was designed with same supply using current-mode technique.