André Crahay

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

The surface texturization of solar cells: A new method using V-grooves with controllable sidewall angles

The bulk recombination mechanisms (such as the Auger recombination, for instance) that prevent the collection of photogenerated carriers are determining the present tendency of designing thinner silicon solar cells. Such an evolution requires light trapping methods in order to keep the average light path to good values. Light trapping can be obtained through surface texturization. A texturization method using a HF-HNO3 solution in an isotropic etching has been investigated. This method has allowed us to obtain a surface of periodic V-grooves with controllable sidewall angles. Beside the fact that this new texturization method of silicon may lead to new light trapping structures, it also shows a simple way to texturize polycrystalline silicon solar cells. A ray tracing program has been devised in order to calculate the average light path for rays having a long wavelength (those rays being not readily absorbed by the Si substrate) and the generated photocurrent (without recombination effects) in cells with varying surface texturization angles.

Nanowire-decorated microscale metallic electrodes.

One of the challenging aspects of science and technology on a nanometer-scale is the precise three-dimensional control of nano-objects. Scanning probe microscopy manipulation, magneticor electric-field alignment and lithography-based techniques are only a few of the techniques that have been reported so far. Nevertheless, most of these techniques are still being developed and their integration for device fabrication represents a real challenge for the scientific community. Within this context, nanowires and nanotubes are of great interest because they lie between the macroscopic and atomic scales. The ability to fabricate andmanipulate such objects in a reliablemanner on a large scale will foster their use in electronic, photonic, and sensing applications. Templatebased methods have been successfully used for nanowire fabrication as they allow the realization of complex organic/ inorganic nanostructures. To date, nanoporous anodic alumina oxide (AAO) made by the electrochemical oxidation of aluminum has been extensively used because it provides a good platform for the development of various nanostructures. This interest originates from the fact that AAO membranes, having a high density of nanopores (up to 10 cm ), are easily produced over large areas with variable thicknesses. Moreover, a good chemical and mechanical stability combined with interesting electrical properties make AAO membranes good candidates for nanowire fabrication. However, the use of such nanostructures as passive or active components in emerging electronic devices requires smartly engineered arrays of nanowires with well defined position and pitch.

Self-aligned silicon-on-insulator nano flash memory device

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal floating gate embedded in the gate oxide. The length, width and height of the nanocrystal are 10, 10 and 20 nm, respectively. As long as the control gate voltage does not exceed +/-2V, the device behaves like a thin and narrow P-channel MOSFET. When a voltage of -5 or +5 V is applied to the control gate at room temperature, holes are injected into the floating gate or removed from it, respectively. This effect induces a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM

Vapour sensitivity of an ALD hierarchical photonic structure inspired by Morpho

The unique architecture of iridescent Morpho butterfly scales is known to exhibit different optical responses to various vapours. However, the mechanism behind this phenomenon is not fully quantitatively understood. This work reports on process developments in the micro-fabrication of a Morpho-inspired photonic structure in atomic layer deposited (ALD) materials in order to investigate the vapour optical sensitivity of such artificial nanostructures. By developing recipes for dry and wet etching of ALD oxides, we micro-fabricated two structures: one combining Al2O3 and TiO2, and the other combining Al2O3 and HfO2. For the first time, we report the optical response of such ALD Morpho-like structures measured under a controlled flow of either ethanol or isopropyl alcohol (IPA) vapour. In spite of the small magnitude of the effect, the results show a selective vapour response (depending on the materials used).

Optimisation and simulation of an alternative nano-flash memory : the SASEM device

Process simulations are performed in order to simulate the full fabrication process of an alternative nano-flash memory in order to optimize it and to improve the understanding of the dot storage formation. The influence of various parameters (oxidation temperature, nanowire shape) have been investigated.

High-efficiency backside contact solar cells with a self-aligned process and new texturization technique for silicon

A self-aligned process for back side contact solar cells has been demonstrated. It requires only one photolithography step without alignment, instead of 4 to 6. As a consequence, the fabrication cost of BSC solar cells has been highly reduced. Also, a texturization method using the HF-HNO/sub 3/ couple in an isotropic etching has been investigated. This method allows to obtain a surface of periodic V-grooves with controllable sidewall angles. This new texturization technique, which may be used with multicrystalline silicon as well, opens the way to a new light trapping structure.