Jean-Pierre Raskin

Nonlinear Properties of Si Based Substrates for Wireless Systems and SoC Integration

The nonlinear behaviour of silicon substrates with different resistivities is analyzed using coplanar structures. In order to compare the nonlinear performance for different substrates and technologies, the harmonic distortion of crosstalk test structures is investigated, as well as the dependence on the distance. The generated harmonic components due to a large signal at 900 MH are measured using a one-tone network analyzer based setup. Below the crosstalk tap, harmonic levels as high as -43 and -54 dBc for 15 dBm are generated for standard and high-resistivity (HR) Si substrate, respectively. The introduction of a trap-rich layer at the interface between the BOX and the high-resistivity Si (HR-Si) provides a reduction of at least 45 dB in the harmonic distortion generated into the substrate. It has been proven that these results can be easily extrapolated to crosstalk structures with different dimensions.

Fabrication and characterization of High Resistivity SOI wafers for RF applications

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed when the substrate surface is passivated with a trap-rich layer of material, such as polysilicon. A technique to fabricate substrate-passivated HR SOI wafer is presented, where the wafers are obtained by bonding a polysilicon-passivated HR Si substrate with an oxidized donor substrate. Preliminary encouraging bonding test results are presented.

Self-formation of sub-10 nm nanogaps based on silicidation

We have developed a simple and reliable method for the fabrication of sub-10xa0nm wide nanogaps. The self-formed nanogap is based on the stoichiometric solid-state reaction between metal and silicon atoms during the silicidation process. The nanogap width is determined by the metal layer thickness. Our proposed method can produce symmetric and asymmetric electrode nanogaps, as well as multiple nanogaps within one unique process step, for potential application to biological/chemical sensors and nanoelectronics, such as resistive switches, storage devices, and vacuum channel transistors. This method provides high throughput and it is suitable for large-scale production.