André Ivanov

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

System-on-Chip: Reuse and Integration

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Design, synthesis, and test of networks on chips

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

BIST for network-on-chip interconnect infrastructures

In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost

Embedded timing analysis: a soc infrastructure

This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure a variety of timing-related SoC characteristics, including jitter. The ETIA requires little design and area overhead and performs accurately under process and environment variation and noise.

On-line fault detection and location for NoC interconnects

A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant performance parameters - power, latency, and throughput. Experiments show that our approach is effective and requires minimal modifications of the existing design methods for NoC interconnects

Jitter models for the design and test of Gbps-speed serial interconnects

We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication links performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER.

A scalable communication-centric SoC interconnect architecture

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. Some of the main problems in the ultra deep submicron technologies arise from nonscalable global wire delays, failure to achieve global synchronization and difficulties associated with nonscalable bus-based functional interconnect. These problems can be dealt with by using a structured interconnect template to design future SoCs. Recently, we introduced the butterfly fat-tree as an overall interconnect architecture, where IPs reside at the leaves of the tree and switches at its vertices. Here, we analyze this architecture with a particular focus on achieving overall timing closure. The only global wires in this routing architecture are the inter-switch wires and the delays in these global wires can be predicted at the initial stages of design cycle. Our analysis shows that the inter-switch wire delay in the networked SoC can be always designed to fit within one clock cycle, regardless of the system size. We contrast the analysis for our network with that of a bus-based architecture. For the latter, we illustrate how the interconnect delay and system size are interrelated, thereby limiting the number of IP blocks that can be connected by a bus.

High-throughput switch-based interconnect for future SoCs

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.

An effective BIST scheme for ROM's

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR. >