Cristian Grecu

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

Design of a switch for network on chip applications

System on Chip (SoC) design in the forthcoming billion transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in the range of 50-100 nm arise from non-scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues, and difficulties associated with non-scalable bus-based functional interconnect. These problems are addressed in this paper by introducing a new design methodology. A switch-based network-centric architecture to interconnect IP blocks is proposed. We introduce a butterfly fat tree architecture as an overall interconnect template. In this new interconnect architecture, switches are used to transfer data between IP blocks. To reduce overall latency and hardware overhead, wormhole routing is adopted. The proposed switch architecture supports this routing method. Initial implementation of the switch reveals that the total switch area is expected to amount to less than 2% of a large SoC.

System-on-Chip: Reuse and Integration

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Design, synthesis, and test of networks on chips

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

BIST for network-on-chip interconnect infrastructures

In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost

On-line fault detection and location for NoC interconnects

A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant performance parameters - power, latency, and throughput. Experiments show that our approach is effective and requires minimal modifications of the existing design methods for NoC interconnects

A scalable communication-centric SoC interconnect architecture

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. Some of the main problems in the ultra deep submicron technologies arise from nonscalable global wire delays, failure to achieve global synchronization and difficulties associated with nonscalable bus-based functional interconnect. These problems can be dealt with by using a structured interconnect template to design future SoCs. Recently, we introduced the butterfly fat-tree as an overall interconnect architecture, where IPs reside at the leaves of the tree and switches at its vertices. Here, we analyze this architecture with a particular focus on achieving overall timing closure. The only global wires in this routing architecture are the inter-switch wires and the delays in these global wires can be predicted at the initial stages of design cycle. Our analysis shows that the inter-switch wire delay in the networked SoC can be always designed to fit within one clock cycle, regardless of the system size. We contrast the analysis for our network with that of a bus-based architecture. For the latter, we illustrate how the interconnect delay and system size are interrelated, thereby limiting the number of IP blocks that can be connected by a bus.

High-throughput switch-based interconnect for future SoCs

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

With the ever-increasing degrees of integration, design of communication architectures for big systems on chip (SoCs) is a challenge. The communication requirements of these large multi processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. To become a viable alternative IC design methodology, the NoC paradigm must address system-level reliability issues, which are among the dominant concerns for SoC design. The basic operations of NoCs are governed by on-chip packet switched networks. On the other hand, incorporation of different coding schemes in SoC design is being investigated as a means to increase system reliability. As NoCs are built on packet-switching, it is very natural to modify the data packets by adding extra bits of coded information to protect against any transient malfunction. By incorporating joint crosstalk avoidance coding (CAC) and forward error correction (FEC) schemes in the NoC data stream we are able to enhance the system reliability and at the same time reduce communication energy

Testing Network-on-Chip Communication Fabrics

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation.