André Leycuras

Stress relaxation during the growth of 3C-SiC∕Si thin films

In this work the authors study the strain of 3C-SiC thin films grown on (001) on-axis silicon substrates. They use ex situ wafer curvature measurements to monitor the residual strain of silicon carbide film. At high temperature creep effects take place and modify the intrinsic strain of silicon carbide film. From the time and temperature dependences of these effects, they determine the creep exponent and the creep activation energy for 3C-SiC. Obtained values of N=2.6±0.3 and Q=5.6±1.0eV are similar to those reported in literature for hexagonal polytypes of silicon carbide.

Heteroepitaxy of GaAs on Si: The effect of in situ thermal annealing under AsH3

This letter shows that an in situ thermal annealing step in AsH3/H2 during the metalorganic vapor phase epitaxy of GaAs on Si(001) improves the crystalline quality. The dislocation density is reduced (below 107 cm−2) without affecting the Si diffusion across the heterointerface or the strain level in the epilayer. The nature of the various near‐band‐gap recombinations present in the unannealed and annealed samples is discussed in light of selective photoluminescence experiments.

Defect‐related Si diffusion in GaAs on Si

Preferential diffusion channels of silicon are evidenced in GaAs grown by metalorganic vapor phase epitaxy on Si(100). The density of these diffusion channels is found to be consistent with the measured dislocation density. In addition, combining scanning electron microscopy and x‐ray fluorescence it is shown that a large amount of Si emerges at the surface inside small 〈011〉 overgrowth oriented defects (≊1 μm) present at the GaAs/Si surface.

Investigation of 2 inch SiC layers grown in a resistively-heated LP-CVD reactor with horizontal “hot-walls”

With respect to more standard and more widely used inductive-heating, the resistivelyheated reactors offer the strong advantage of low cost, easy installation and low running constraints. Combined with an easy adaptation to the increasing size of wafers, this results in very strong advantages. This simple technique was mainly restricted to the growth of small size samples for academic purpose [1]. In this work we report an investigation of 2 inch SiC layers deposited in a new, horizontal and resistively-heated, “hot-wall” LP-CVD reactor specially designed for large flexibility. Introduction Due to superior physical properties, SiC appears as a most promising material for high power, high frequency and high temperature electronic devices or sensors. In this case, whatever is the targeted application, one needs to deposit a low doped, electronic grade material, on a large diameter single crystalline wafer. A promising technique is the use of hot-wall CVD, coupled with resistive heaters. With respect to the more standard and widely used inductive-heating technology, a resistivelyheated reactor offers advantages in terms of (low) cost, (easy) installation and (low) running constraints. Combined with a very easy adaptation to the increasing size of wafers, this seems very appealing. Unfortunately, up to now, this simple technique has been restricted to the growth of small size samples for academic purpose [1] and was not seriously considered for industrial applications. In order to establish more the potentiality of this system, we report a detailed investigation of the thickness uniformity, surface morphology and low temperature photoluminescence properties of a series of epitaxial layers deposited on silicon. We show that, on 2” Si substrates, state of the art material can be easily obtained. Experimental The reactor has been specially designed to allow, both, usual SiC growth by LP-CVD [1] as well as full Si-wafer conversion by LPE [2]. In this case, the control of the vertical temperature gradient is essential to insure an optimised liquid phase diffusion. This technical constraint dictated the choice of two independent heaters (upper and lower resistive) forming then a standard“hot-walls” configuration. The walls are thin (0.5mm) and made of high purity graphite sheets. The thermal inertia is then very low, which allows RTP (Rapid Thermal Processing) to be done up to 1800°C. In order to Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 273-276 doi:10.4028/www.scientific.net/MSF.457-460.273

Evidence by Raman spectroscopy and x‐ray diffraction of a strong influence of H2O traces on the metalorganic vapor phase epitaxy of GaAs on Si

The metalorganic vapor phase epitaxy of GaAs on Si is shown to be strongly sensitive to the residual water vapor content in the growth reactor atmosphere. This finding is evidenced both by Raman spectroscopy and double‐crystal x‐ray diffraction. For the growth of good crystalline quality GaAs on Si, the upper hygrometric level limit is found around 0.5 ppm by volume.

INFLUENCE OF MOVPE GROWTH-PARAMETERS ON THE STRUCTURAL AND OPTICAL-PROPERTIES OF GAAS ON SI(100)

Abstract The influence of various parameters such as the initial low temperature buffer layer and layer thickness on the overall MOVPE-grown GaAs on Si crystal properties has been investigated. An accurate control of the initial buffer layer, nucleating as a three-dimensional island on Si (TEM results), induces a substantial defect reduction in GaAs on Si epilayers. Further defect reduction is achieved by in-situ high temperature annealing (850°C) under AsH 3 /H 2 flow during growth. No change of the silicon cross diffusion profile (SIMS) or residual stress magnitude was observed, in contrast with post-growth annealing processes which are shown also to affect detrimentally the optical properties. Moreover, the modification of the main residual acceptor species and the (100) coplanar tensile stress in GaAs on Si is discussed in the light of photoluminescence spectroscopy.

Role of arsenic in the heteroepitaxy of Ge/GaAs

During the heteroepitaxy of Ge on GaAs, arsenic diffuses from the GaAs substrates and hence is present in the Ge epilayer. It has been shown that As is incorporated into the layer but also segregated to the surface. The Ge growth is monitored in situ by laser reflectometry, and it gives the thickness, the growth rate, and the morphology of the layer. It is shown here that a too large surface concentration of As due to intentional doping can block the Ge growth. Atomic force micrographs of the morphological defects (pyramidlike void and large steps) suggest that these defects are due to local segregated excess As concentrations caused by the step advance. It is shown that the density of defects as well as the thickness at which they appear are characterized by the same activation energy of ∼1 eV.

Preferential carbon etching by hydrogen inside hexagonal voids of 6H-SiC(0001)

6H-SiC(0001) samples have been etched in a hot-wall chemical vapor deposition reactor at a hydrogen pressure of 13 mbar at 1800 ° C . The surface morphology and elemental composition have been studied by scanning electron microscopy and micro-Auger analysis. Stoichiometric etching of SiC with equal atomic concentrations of Si and C is found on the flat sections of the surface, but in hexagonal voids of the SiC samples, a selective removal of C, leading to a pure Si surface at the bottom of the voids, is observed. Fast gas diffusion is the main transport mechanism for etching of the flat surface, while Knudsen diffusion becomes important inside the voids. It is proposed that the lower diffusion constant of reaction products containing Si compared to those containing C, leads to a preferential removal of C and a Si enrichment inside the voids.

ROLE OF OXYGEN IN THE FORMATION OF VOIDS AT THE SIC-SI INTERFACE

The purpose of this letter is to observe voids at the SiC–Si interface beneath the SiC layers grown by chemical vapor deposition at high temperature. It is shown in this letter that the volume of the voids per unit area is proportional to the oxygen concentration in the Si substrate over seven orders of magnitude. In situ dynamical reflectivity measurements show that the voids are formed during the carbonization step and especially when the carbon, which has diffused deeply into the Si substrate, diffuses back toward the SiC layer just completed at the substrate surface. This back diffusion is due to the inversion of the carbon concentration gradient sign at that moment. It is accompanied by the formation of CO, resulting either from the reduction of SiO or SiO2 dissolved in the Si substrate. Diffusion of carbon in silicon might improve the methods of purification for the removal of oxygen which remains the main impurity of the purest silicon material.

Flash Lamp Supported Deposition of 3C-SiC (FLASiC) – a Promising Technique to Produce High Quality Cubic SiC Layers

This paper summarises latest advancements regarding FLASiC (Flash lamp supported deposition of 3C-SiC) as a new approach to produce high quality SiC-Si heteroepitaxial material. This concerns description of the process and equipment, microstructural results and modelling aspects. In this manner a new era of nanoscale liquid phase epitaxy could be born. Introduction The production of cubic SiC (3C-SiC) layers in device quality through the epitaxial growth on (100) Si wafers has remained a challenging task yet. Remembering back the last bigger effort it was at the ICSCRM ́95 at Kyoto that several groups presented their latest results regarding high quality material and discussed lively how to overcome the main problem: the high defect density of the SiC layer. Since then there has been not too much progress reported. Recently it was demonstrated that the use of Flash Lamp Processing (FLP) can support the production of high quality 3C-layers in a promising manner [1]. This process got the acronym FLASiC standing for Flash LAmp Supported Deposition of 3C-SiC [2].The FLASiC team –see the author and affiliation list aboveorganized within a project of the V. Framework of the European Community is currently extending this early work as a broader approach with the following main aspects: (i) Development of the epitaxial process including FLP: This includes not only the development of FLASiC as a basic version, but also the so-called i-FLASiC process [2] as the latest variant to overcome some problems of the basic FLASiC. In this case the ”i” stands for “inverse”, see below. (ii) Development of a prototype equipment for the FLP: Flash lamp processing or simply annealing was an early outcome of the euphoria in Laser annealing of semiconducting materials in the late seventies. The difference of FLP to Laser annealing is the longer annealing time in the msec Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 175-180 doi:10.4028/www.scientific.net/MSF.457-460.175