Andre Vandemeulebroecke

A CMOS 13-b cyclic RSD A/D converter

A 13-b CMOS cyclic A/D converter that does not need trimming nor digital calibration is presented. The effects associated with the error on the gain factor 2 as well as the offset errors are corrected by taking full advantage of the redundant signed digit (RSD) principle. The gain error resulting from mismatches among switched capacitors is corrected by a novel strategy that implements an exact multiplication by four after two cycles. As a result, offset errors do not affect the integral or the differential linearities from the RSD algorithm. The remaining overall shift caused by offsets is reduced under the LSB level by a proper choice of capacitor switching sequence. The converter achieves 1/2 LSB integral and differential linearity at 25 kS/s; harmonic distortion is less than -83 dB. Chip area is 2.9 mm2 in a standard CMOS 3-mu-m technology, including control logic and the serial-to-parallel output shift register. Power consumption is 45 mW under +/-5-V supplies.

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >

Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm

An implementation of a VLSI fully interconnected neural network with only two binary memory points per synapse is described. The small area of single synaptic cells allows implementation of neural networks with hundreds of neurons. Classical learning algorithms like the Hebbs rule show a poor storage capacity, especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connection; an algorithm for programming a Hopfield neural network as a high-storage content-addressable memory is proposed. The storage capacity obtained with this algorithm is very promising for pattern-recognition applications. >

A high-storage capacity content-addressable memory and its learning algorithm

J.J. Hopfields neural networks (1982) show retrieval and speed capabilities that make them good candidates for content-addressable memories (CAMs) in problems such as pattern recognition and optimization. A novel implementation is presented of a VLSI fully interconnected neural network with only two binary memory points per synapse (the connection weights are restricted to three different values: +1, 0 and -1). The small area of single synaptic cells (about 10/sup 4/ mu m/sup 2/) allows the implementation of neural networks with more than 500 neurons. Because of the poor storage capability of D. Hebbs learning rule (1949), especially in VLSI neural networks where the range of the synapse weights is limited by the number of memory points contained in each connection, a novel algorithm is proposed for programming a Hopfield neural network as a high-storage-capacity CAM. The results of the VLSI circuit programmed with this algorithm are very promising for pattern-recognition applications. >

A single chip 1024 bits RSA processor

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 μm CMOS process and 500 mW at 25 MHz).

A New Carry Free Division Algorithm and Application to a Single Chip 1024 bits RSA Processor

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation. Its application to a 1024 bits RSA cryptographic chip will also be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 ¿m CMOS process and 500 mW at 25 MHz).

Comparison of equivalent precision dedicated FFT processors

A study of the quantization noise in FFT (fast Fourier transform) processors is undertaken with the purpose of comparing several possible Si implementations. Simulations are presented to validate theoretical results and to derive corrected formulas, that predict simulation results within 0.5 dB. Finally, a comparative study shows that application-specific integrated circuits using fixed-point arithmetic with truncation represent the best compromise for real-time integrated FFTs.<<ETX>>