Cristiano Azzolini

Integrated lock-in amplifier for contactless interface to magnetically stimulated mechanical resonators

The design of an integrated lock-in amplifier is discussed, specifically conceived for the detection of low-level signals at a harmonic of the drive frequency in magnetically excited resonant structures. The circuit includes in-phase and quadrature analogue signal processing channels, whose outputs feed an integrated SigmaDelta analogue to digital converter. The circuit can be operated in different configurations, depending on the application requirements: in particular, by combining the digitized outputs of the two channels, vector operation can be obtained. The entire analogue chain, including the SigmaDelta modulator, was designed using fully differential elaboration. The circuit was developed in a 0.35 mum, dual poly-Si, four metal layers analogue CMOS technology with high resistivity poly-Si option. Performance based on transistor-level simulations are provided.

A 1-V CMOS audio amplifier for low cost hearing aids

The paper describes a very low-cost analog audio amplifier IC for hearing aid devices. The amplifier employs an effective offset cancellation analog circuit aimed to ensure a low quiescent consumption even in case of strong mismatch due to silicon manufacturing. The consumption is 500-muA from a 1.3-V battery supply (excluded mic/loudspeaker biasing) but the hearing aid can operate down to 1-V. Measurements confirm that the nominal THD of the circuit is lower than 1-% at 10-mW output power. The die area (including pads) is lower than 1.5-mm2 in a standard 0.35-mum CMOS process (high-res poly option).

100-MS/s 14-b track-and-hold amplifier in 0.18-/spl mu/m CMOS

The paper describes the design and the implementation of a track-and-hold (THA) amplifier suitable for a 14-b, 100 MS/s A/D converter, in 0.18 /spl mu/m CMOS technology. The THA is based on the flip-around architecture with telescopic cascode OTA. Adequate settling behavior was achieved by means of accurate analysis and design of the boosting amplifier with respect to its impact on the pole-zero placement. A modified bootstrap switch featuring a high linearity and reduced complexity is also presented.

Very low-cost CMOS audio amplifier for 1-V portable applications

The design of a very low-cost full-analog audio amplifier IC for hearing aid devices is presented. The overall circuit consumes 460-muA from a 1.3-V battery supply (excluded loudspeaker, without signal) but the hearing aid is able to operate with a depleted battery down to 1-V. The nominal THD of the circuit is lower than 1-% at 10-mW output power whereas the input referred equivalent noise voltage is 3.2-muVRMS. An effective analog offset cancellation circuit ensures a low quiescent power consumption in case of strong process mismatch. The silicon area is as low as 1.5-mm2 in a 0.35-mum CMOS process.

Design of a 2-GS/s 8-b self-calibrating ADC in 0.18 /spl mu/m CMOS technology

The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-/spl mu/m CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented.

BiCMOS vs. CMOS Operational Amplifiers for High-Speed Pipelined A/D Converters

This paper presents a comparison between BiCMOS and CMOS op-amps to be employed in pipelined analog-to-digital converters. Single and two-stage architectures were considered; in addition, a couple of op-amps exploiting bipolar devices in the input stage are proposed. The amplifiers were designed for the first stage of a 12-b high-speed converter; op-amps are constrained by a fixed power budget and are compared in terms of the error due to their finite DC-gain and incomplete settling.

Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers

A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).

High-level Accurate Model of High-resolution Pipelined ADC's

This paper describes an accurate model for the systematic design and the simulation of high-resolution pipelined ADCs. The design is based on the non-linearities affecting the ADC whereas the goal is the evaluation of the best architecture matching the specifications (DNL and INL). Bit partitioning along pipeline chain, amplifiers specifications (designed down to transistor-level in both CMOS and BiCMOS technologies), capacitors size, power consumption and calibration requirements are delivered. An integrated simulation tool allows the performances evaluation of the converter. The complete design suite was implemented in MATLAB

Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCs

The paper presents a digital foreground calibration technique for pipeline analog-to-digital converters (ADCs). While the conventional calibration approach requires additional buffered voltage references, the proposed technique requires only a voltage reference, already available in the converter, thus allowing a significant circuit simplification and silicon area savings. Since the number of buffered voltage references in the conventional calibration algorithm increases exponentially with the resolution of the conversion stages to be calibrated, the proposed technique is suitable for high-resolution, high-speed pipeline ADCs.