Andrea Domenici

Replica Management in the European DataGrid Project

Within the European DataGrid project, Work Package 2 has designed and implemented a set of integrated replica management services for use by data intensive scientific applications. These services, based on the web services model, enable movement and replication of data at high speed from one geographical site to another, management of distributed replicated data, optimization of access to data, and the provision of a metadata management tool. In this paper we describe the architecture and implementation of these services and evaluate their performance under demanding Grid conditions.

Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries

This paper presents a novel charge equalization technique seamlessly integrated into a modular Battery Management System (BMS) for lithium-ion (Li-ion) batteries. The charge equalizer is a crucial element for an effective use of a Li-ion battery consisting of many series-connected cells. We describe a fully distributed charge equalizer based on a circular balancing bus, which outperforms other recently published approaches. Its safety requirements have formally been verified using a model checker, showing that formal methods and, in particular, the Symbolic Analysis Laboratory environment, can be effective to verify the safety requirements of a BMS.

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) sensitivity of their designs. In this paper, we present an accurate simulation method for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs. The approach is able to simulate SEUs affecting the configuration memory of both logic and routing resources since it is able to accurately model the electrical behavior of SEUs in the configuration memory. Detailed experimental results on a large set of benchmark circuits are provided and the comparison with fault injection experiments is shown in order to validate the accuracy of the proposed method. The results clearly demonstrate the benefits of our approach since simulation results predict almost completely the results obtained through fault injection.

SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies

As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPGA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.

Failure probability of SRAM-FPGA systems with Stochastic Activity Networks

We describe a simulation-based fault injection technique for calculating the probability of failures caused by SEUs in the configuration memory of SRAM-FPGA systems. Our approach relies on a model of FPGA netlists realised with the Stochastic Activity Networks (SAN) formalism. We validate our method by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed technique by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.

SEU-X: A SEu un-excitability prover for SRAM-FPGAs

We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported.

HRT-UML: taking HRT-HOOD onto UML

This paper discusses issues that arose in an effort to transpose the semantic and methodological value of HRT-HOOD into a carefully-crafted selection of the UML meta-model. The main goal of the project was to prevent the massive advent of theUMLfrom obliterating the unique strengths of theHRTspecialisation of HOOD for the support of real-time design. Avoidance of closed conservatism also afforded the project the opportunity to reflect on aspects of object-oriented design that may arguably benefit the resulting HRT-UML method.

A protocol for resource locking and deadlock detection in a multi-user environment

Abstract In this paper we present a protocol for file locking and deadlock detection in a multi-user Ada environment. It ensures integrity of files concurrently accessed by several tasks belonging either to the same or to distinct Ada programs. In the event of a deadlock, the task responsible for the deadlock can be detected and aborted. When a task within the same program attempts to communicate with the aborted task, an exception is raised in the calling task. In this way, the programmer can define different recovery strategies by providing appropriate exception handlers.

Verifying safety properties of a nonlinear control by interactive theorem proving with the Prototype Verification System

Interactive, or computer-assisted, theorem proving is the verification of statements in a formal system, where the proof is developed by a logician who chooses the appropriate inference steps, in turn executed by an automatic theorem prover. In this paper, interactive theorem proving is used to verify safety properties of a nonlinear (hybrid) control system. Interactive theorem proving is the verification of assertions with the assistance of an automatic theorem prover.Formal verification is an important tool in the development of control systems.In this paper, the PVS (Prototype Verification System) is used to prove properties of the level control of a storage tank.

High availability using virtualization

High availability has always been one of the main problems for a data center. Till now high availability was achieved by host per host redundancy, a highly expensive method in terms of hardware and human costs. A new approach to the problem can be offered by virtualization. Using virtualization, it is possible to achieve a redundancy system for all the services running on a data center. This new approach to high availability allows the running virtual machines to be distributed over a small number of servers, by exploiting the features of the virtualization layer: start, stop and move virtual machines between physical hosts. The 3RC system is based on a finite state machine, providing the possibility to restart each virtual machine over any physical host, or reinstall it from scratch. A complete infrastructure has been developed to install operating system and middleware in a few minutes. To virtualize the main servers of a data center, a new procedure has been developed to migrate physical to virtual hosts. The whole Grid data center SNS-PISA is running at the moment in virtual environment under the high availability system.