Luca Cassano
University of Pisa
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Publication
Featured researches published by Luca Cassano.
IEEE Transactions on Industrial Informatics | 2014
Federico Baronti; Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Roberto Roncella; Roberto Saletti
This paper presents a novel charge equalization technique seamlessly integrated into a modular Battery Management System (BMS) for lithium-ion (Li-ion) batteries. The charge equalizer is a crucial element for an effective use of a Li-ion battery consisting of many series-connected cells. We describe a fully distributed charge equalizer based on a circular balancing bus, which outperforms other recently published approaches. Its safety requirements have formally been verified using a model checker, showing that formal methods and, in particular, the Symbolic Analysis Laboratory environment, can be effective to verify the safety requirements of a BMS.
defect and fault tolerance in vlsi and nanotechnology systems | 2012
Cinzia Bernardeschi; Luca Cassano; Andrea Domenici; Luca Sterpone
SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) sensitivity of their designs. In this paper, we present an accurate simulation method for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs. The approach is able to simulate SEUs affecting the configuration memory of both logic and routing resources since it is able to accurately model the electrical behavior of SEUs in the configuration memory. Detailed experimental results on a large set of benchmark circuits are provided and the comparison with fault injection experiments is shown in order to validate the accuracy of the proposed method. The results clearly demonstrate the benefits of our approach since simulation results predict almost completely the results obtained through fault injection.
Journal of Computer Science and Technology | 2015
Cinzia Bernardeschi; Luca Cassano; Andrea Domenici
As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPGA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.
design and diagnostics of electronic circuits and systems | 2011
Cinzia Bernardeschi; Luca Cassano; Andrea Domenici
We describe a simulation-based fault injection technique for calculating the probability of failures caused by SEUs in the configuration memory of SRAM-FPGA systems. Our approach relies on a model of FPGA netlists realised with the Stochastic Activity Networks (SAN) formalism. We validate our method by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed technique by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.
international on-line testing symposium | 2012
Cinzia Bernardeschi; Luca Cassano; Andrea Domenici
We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported.
design, automation, and test in europe | 2013
Luca Cassano; Dario Cozzi; Sebastian Korf; Jens Hagemeyer; Mario Porrmann; Luca Sterpone
Partially reconfigurable systems are more and more employed in many application fields, including aerospace. SRAM-based FPGAs represent an extremely interesting hardware platform for this kind of systems, because they offer flexibility as well as processing power. In this paper we report about the ongoing development of a software flow for the generation of hard macros for on-line testing and diagnosing of permanent faults due to radiation in SRAM-FPGAs used in space missions. Once faults have been detected and diagnosed the flow allows to generate fine-grained patch hard macros that can be used to mask out the discovered faulty resources, allowing partially faulty regions of the FPGA to be available for further use.
design, automation, and test in europe | 2016
Luca Cassano; Antonio Miele
Dynamic Reliability Management solutions are often adopted in multi-core systems to mitigate aging and wear-out effects, by opportunely distributing the workload on the available cores. The efficiency of such solutions is generally evaluated by considering only the occurrence of the first core failure due to the computational complexity. In this paper we propose an in-depth analysis of such approaches by considering the occurrence of multiple subsequent core failures, thus offering a more precise estimation of the lifetime reliability. In particular, we analyzed two classical load distribution approaches: a load balancing strategy versus a strategy based on spare resources. Experimental results show benefits and limitations of the considered solutions in terms of lifetime reliability while fulfilling system performance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2015
Luca Cassano; Paolo Garza; Elisa Quintarelli; Fabio Salice
Functional diagnosis for complex systems can be a very time-consuming and expensive task, trying to identify the source of an observed misbehavior. We propose an automatic incremental diagnostic methodology and CAD flow, based on data mining (DM). It is a model-based approach that incrementally determines the tests to be executed to isolate the faulty component, aiming at minimizing the total number of executed tests, without compromising 100% diagnostic accuracy. The DM engine allows for shorter test sequences with respect to other reasoning-based solutions (e.g., Bayesian belief networks), not requiring complex pre and post-conditions management. Experimental results on a large set of synthetic examples and on three industrial boards substantiate the quality of the proposed approach.
defect and fault tolerance in vlsi and nanotechnology systems | 2014
Luca Cassano
Incremental functional diagnosis is the process of iteratively selecting a test, executing it and based on the collected outcome deciding either to execute one more test or to stop the process since a faulty candidate component can be identified. The aim is to minimise the cost and the duration of the diagnosis process. In this paper we compare six engines based on machine learning techniques for driving the diagnosis. The comparison has been carried out under a twofold point of view: on the one hand, we analysed the issues related to the use of the considered techniques for the design of incremental diagnosis engines; on the other hand, we carried out a set of experiments on three synthetic but realistic scenarios to assess accuracy and efficiency.
IEEE Sensors Journal | 2014
Daniel Cesarini; Luca Cassano; Marijan Kuri; Vedran Bilas; Marco Avvenuti
Automatic weather stations (AWSs) are widely used for an environmental sensing in harsh environments such as Antarctica, high mountains, and deserts. As these systems are often deployed far from mains power sources, they are usually equipped with rechargeable batteries and energy harvesting systems. Predeployment configuration of an AWS is a challenging task, as designers have to face with contrasting energy-related choices, the correct tradeoff of which determines the success of the AWSs mission and its survivability. Among them, the most effective are the energy harvesting technology, size of the battery, and frequency of sensing and communication. In this paper, we describe AENEAS, an energy-aware simulator of AWSs that allows designers to assess the impact of hardware and software choices on the energy evolution of the system. The tool is extensively configurable, thus enabling the simulation of a large number of hardware configurations as well as of the sensing and communication applications running on the AWS. The simulator has been validated by comparing results computed by AENEAS with data collected from two real-world AWSs installed on an alpine glacier and in a urban environment, obtaining a high accuracy in both cases. A number of use cases are discussed to demonstrate how AENEAS can be used to assess the impact on the energy behavior of the AWS of different batteries, energy harvesters, and application behaviors.