Andrea Francini

Minimum-delay self-clocked fair queueing algorithm for packet-switched networks

The minimum-delay self-clocked fair queueing (MD-SCFQ) algorithm that we present in this paper is the first algorithm that achieves the same delay bounds as the packet by packet version of generalized processor sharing (P-GPS), has fairness properties similar to P-GPS, and uses a system-potential function of 0(1) complexity. To prove that MD-SCFQ achieves the same delay bounds of P-GPS, we have shown that the fluid version of MD-SCFQ belongs to the class of rate proportional server (RPS) schedulers; thus, its packet-by-packet version inherits all the well-known single-node and multiple-node delay properties of P-RPS schedulers. We have also computed the fairness index of MD-SCFQ, and show that is very close to that of P-GPS. Because of the properties of its system potential, MD-SCFQ, when combined with a shaper which declares packets eligible for scheduling according to their virtual starting times, is a work-conserving worst-case fair scheduler.

Implementing fair queueing in ATM switches: the discrete-rate approach

The total implementation cost of schedulers which approximate the generalized processor sharing (GPS) policy is dominated by the complexity of maintaining and sorting the time-stamps for all connections. Several approaches have been proposed which reduce the cost of the sorting operation and only introduce a small degradation in the delay bounds of the scheduler; they include logarithmic calendar queues and schedulers supporting a discrete set of guaranteed rates. All these techniques still require computing and storing one time-stamp per connection, thus maintaining the cost of GPS-related algorithms clearly higher than that of less sophisticated schedulers. Furthermore, in the case of the discrete-rate approach, the complexity increases linearly with the number of supported rates, thus making it attractive only for relatively small numbers of rates. In this paper, we introduce a discrete-rate GPS-related scheduler which does not require the computation and storage of one time-stamp per connection, and only maintains a single time-stamp per rate. The elimination of the per-connection time-stamps has no negative effect on the delay bounds. Then, we present a generalized discrete-rate approach, which uses a given number of FIFO queues to support a larger number of guaranteed rates, and only introduces a modest degradation in delay bounds for certain rates. The technique can be applied to our no-per-connection-time-stamp scheduler, as well as to any discrete-rate scheduler.

Implementing fair queueing in ATM switches. I. A practical methodology for the analysis of delay bounds

The minimization of the implementation cost of cell schedulers which aim at approximating the generalized processor sharing (GPS) policy is a key practical issue in next-generation ATM switches. The total complexity of a GPS-related scheduler is a combination of the complexity of its system-potential function and the complexity involved in sorting the timestamps in order to select which cell should be transmitted. Several scheduling disciplines using a system-potential function of O(1) complexity have previously been introduced; still, the task of sorting the timestamps makes the cost of implementing a GPS-related scheduler quite significant. Thus, in practice, approximations are often introduced in the scheduler to reduce implementation complexity, typically at the cost of some degradation in the delay properties of the scheduler. In order to optimize the design so that such degradations are minimized, a tool is necessary, in the form of a general methodology to promptly and accurately analyze the delay properties. To truly aid in the design of the scheduler, such methodology should be simple to use in all practical situations. We present a methodology that fulfills this need. In the case of leaky-bucket constrained sources, we explicitly derive a general result for the delay bounds; our methodology, however, is applicable to other source models.

Providing QoS guarantees in packet switches

The continuous growth in the demand for diversified quality-of-service (QoS) guarantees in broadband networks introduces new challenges in the design of next-generation packet switches. Packet scheduling is the most critical function involved in the provision of individual bandwidth and delay guarantees to the switched flows. Most of the scheduling techniques proposed so far assume the presence in the switch of a single contention point, residing in front of the outgoing links. Such an assumption is not consistent with many popular switch architectures, which typically have multiple contention points, located in both ingress and egress port cards, as well as in the fabric itself. We define a distributed scheduling architecture to provide differentiated QoS guarantees to individual traffic flows in a switch with multiple contention points. Our scheduling architecture is simple to implement, since it keeps per-flow scheduling confined to the port cards, and is suitable for applications in QoS frameworks for both IP and ATM networks.

Enhanced weighted round robin schedulers for accurate bandwidth distribution in packet networks

Abstract Weighted round robin (WRR) schedulers constitute a popular solution for differentiating the bandwidth guarantees of heterogeneous IP flows, mostly because of their minimal implementation cost. However, the existing WRR schedulers are not sufficient to satisfy all the requirements of emerging quality-of-service frameworks. Flexible bandwidth management at the network nodes requires the deployment of hierarchical scheduling structures, where bandwidth can be allocated not only to individual flows, but also to aggregations of those flows. With currently available WRR schedulers, the superimposition of a hierarchical structure compromises the simplicity of the basic scheduler. WRR schedulers are also known for their burstiness in distributing service, which exposes the scheduled flows to higher packet-loss probability at downstream nodes. By construction, WRR schedulers distribute bandwidth proportionally to the service shares allocated to the individual flows. For best-effort (BE) flows, having no specified bandwidth requirements, existing WRR schedulers typically allocate arbitrary service shares. This approach conflicts with the intrinsic nature of BE flows and reduces the availability of bandwidth for the allocation of guaranteed-bandwidth (GB) flows. We present three enhancements for WRR schedulers that solve these problems. In the first enhancement, we superimpose a “soft” scheduling layer on the basic WRR scheduler by simply redefining the computation of the flow timestamps. The second enhancement substantially reduces the service burstiness of the WRR scheduler with only marginal impact on its implementation cost. Finally, the third enhancement allows the smooth integration of GB and BE flows, with efficient management of the available bandwidth and total compliance with the nature of BE flows.

Performance analysis of large multicast switches with multicast virtual output queues

In multicast switches, the accommodation of multicast traffic in multiple queues per input buffer reduces the throughput degradation caused by head-of-line (HOL) blocking. Such an arrangement, called multicast virtual output queuing (MC-VOQ), is very promising in theory but can only be implemented in practice with heavy approximation. Complete avoidance of the HOL blocking problem would in fact require a distinct queue for each fanout set possible, leading to an exponential growth of the number of queues needed with the switch size. If only a limited number of queues can be used per input buffer, criteria must be identified for setting the number of queues, for associating the fanout sets with the individual queues, and for scheduling the transmission of packets out of the queues. This paper presents an analytical model for the investigation of saturation throughput and packet delay in MC-VOQ multicast switches. The model relies on the assumption of Poisson-distributed uniform input traffic and random queuing and scheduling policies. Extensive simulation experiments validate the results of the analysis for large switch sizes.

Feedback control in a distributed scheduling architecture

Multiple-module, multistage packet switching systems are gaining popularity as a scalable solution to the ever increasing demand for the aggregate switching capacity. Due to additional contention points between the stages, such systems differ in their behavior from single module output buffered switches, which serve as a model for most of the advanced quality of service (QoS) scheduling algorithms. Recently, a distributed scheduling reference architecture has been proposed to extend the QoS provisioning framework to the practical multistage switches. While keeping all the per-flow state information in the port card, it aggregates the individual traffic flows into a few QoS based fabric channels and relies on the intelligent selective feedback to ensure that the QoS guarantees of the individual flows are met. In this paper we discuss a novel credit-based feedback mechanism that allows to aggregate multiple traffic components with diverse QoS requirements into the same downstream FIFO queue. We specifically apply it to merge the guaranteed-bandwidth (GB) and best-effort (BE) QoS channels of the distributed scheduling architecture into a single non-guaranteed-delay queue in the switch fabric. The mechanism allows to satisfy the bandwidth requirements of the GB traffic while maximizing the throughput of the BE traffic and distributes the available excess bandwidth between different types of traffic fairly. The presentation is supported by fluid stationary analysis and packet-level simulations.

A family of ASIC devices for next generation distributed packet switches with QoS support for IP and ATM

The protocol-independent (/spl pi/) family of ASIC devices, which we present in this paper, allows to build cost-effective IP routers and ATM switches capable of providing sophisticated Quality-of-Service (QoS) guarantees in the form of throughput, delay and jitter to individual flows or to aggregation of flows. The new chipset, which represents the evolution of the widely used ATLANTA chipset, comprises five devices. The devices presented considerable design and verification challenges, due to the complexity and required speed of the desired QoS functionality. To solve these challenges, we devised a number of design techniques, as well as a novel ad-hoc verification approach.

A low-cost architecture for the implementation of worst-case-fair schedulers in ATM switches

The discrete-rate approach has been proposed in Bennett et al. (1997) as a low-complexity solution for the implementation of worst-case-fair schedulers which approximate the generalized processor sharing (GPS) policy in ATM systems. The total implementation cost with this approach is even competitive with the cost of non-worst-case-fair schedulers implemented with conventional priority queues. Two discrete-rate techniques have been proposed. The one presented in Bennett et al. achieves near-optimal delay and fairness properties, but the discrete-rate scheduler needs to maintain a timestamp for each connection, which significantly contributes to the total cost. The second technique, presented in Chiussi and Francini (1998), does not require per-connection timestamps, and thus further reduces complexity; however, although the scheduler achieves near-optimal delay bounds and is worst-case fair, its fairness in distributing excess bandwidth is compromised. In this paper, we introduce a new discrete-rate technique for reducing the implementation cost of worst-case-fair GPS-related schedulers in ATM systems while maintaining near-optimal performance; the technique uses only a single bit per connection, and achieves delay bounds and fairness indices that are identical to the ones of the discrete-rate scheduler using per-connection timestamps. The new technique works well with the generalized discrete-rate approach presented in Chiussi and Francini to increase the number of discrete rates that the scheduler can support.

Interaction of AQM schemes and adaptive streaming with Internet traffic on access networks

We tested AQM techniques on their ability to influence end-user QoE, especially HTTP Adaptive Streaming (HAS) based video traffic on fixed access networks. Using ns-2 we built a set of simulation scenarios for realistic Internet traffic. Based on data from recent Internet measurements, there are three major types of traffic flowing through the Internet: HTTP web traffic; HAS video traffic and progressive download (PD) video traffic. We modeled HTTP web traffic using Internet statistics published by Google. We generated dynamic HAS traffic by implementing a HAS client. We modeled PD video traffic using statistics from Youtube. We used published research to convert data from simulation traces into QoE metrics. We used realistic mixes of the three types of traffic with different loading conditions to test Random Early Detection (RED), CoDel and Tail-drop queuing on DSL access networks. We also tested various options in HAS for their impact on its QoE. Most AQM configurations improved the QoE metrics of HAS and web traffic. They improved fairness among HAS streams, avoided HAS underflow in a majority of the cases where it would occur with Tail-drop, and tangibly reduced the latency for web page downloads. Sensitivity analysis with RED parameters confirmed that the improved QoE of HAS and web traffic was relatively insensitive to the exact RED parameter set.