Denis A. Khotimsky

Hop-by-hop routing with node-dependent topology information

This paper is focused on the problem of hop-by-hop routing in a network where different nodes have different views of the network topology. In particular, each node may be aware of just a subset of the network links, perceiving the rest as if their cost was infinite. We formalize the idea of nodes individual view of the network with the concept of visibility sets and introduce a routing approach based on the notion of a feasible path, i.e., such path in the nodes visibility set that satisfies certain specified restrictions. It is shown that, in a network with general visibility sets, forwarding the packet along an optimal feasible path is necessary and sufficient to guarantee its eventual delivery to destination without being dropped or routed to the same node twice. Based on the proposed approach, we derive the precise routing policy and formulate an efficient algorithm to search for a family of one-to-all optimal feasible paths in a network with embedded visibility sets. We then proceed to prove the correctness of the algorithm. The new routing method provides for execution of multiple dynamic routing protocols, possibly overlaying each other in the same address space, within a network with common kinds of metrics of arbitrary complexity. It solves the problem of interoperability when new metrics or novel link properties are being introduced and eliminates the necessity to run different protocols and protocol versions within disjoint routing domains.

Generalized inverse multiplexing of switched ATM connections

Inverse multiplexing for ATM (IMA) has been standardized by the ATM Forum to provide a high-capacity logical link by grouping several lower-capacity physical links. IMA is intrinsically point-to-point, assumes congestion-free links, and only tolerates relatively constant differential delays between the links. In this paper, we generalize the notion of inverse multiplexing by introducing switching and buffering within the inverse multiplexed segment. The new scheme, which we call Switched Connection Inverse Multiplexing for ATM (SCIMA) allows to implement an N/spl times/N switch with ports operating at rate kR by using a kN/spl times/kN core ATM switch with ports of rate R. SCIMA executes demultiplexing on a selected set of virtual connections, dynamically distributes their traffic onto a group of switching paths, and performs egress re-assembly using an asynchronous method for differential delay compensation. The scheme is simple to implement, has low overhead, is robust in presence of cell loss within the switch, handles congestion, and tolerates wide variations in differential delays.

Feedback control in a distributed scheduling architecture

Multiple-module, multistage packet switching systems are gaining popularity as a scalable solution to the ever increasing demand for the aggregate switching capacity. Due to additional contention points between the stages, such systems differ in their behavior from single module output buffered switches, which serve as a model for most of the advanced quality of service (QoS) scheduling algorithms. Recently, a distributed scheduling reference architecture has been proposed to extend the QoS provisioning framework to the practical multistage switches. While keeping all the per-flow state information in the port card, it aggregates the individual traffic flows into a few QoS based fabric channels and relies on the intelligent selective feedback to ensure that the QoS guarantees of the individual flows are met. In this paper we discuss a novel credit-based feedback mechanism that allows to aggregate multiple traffic components with diverse QoS requirements into the same downstream FIFO queue. We specifically apply it to merge the guaranteed-bandwidth (GB) and best-effort (BE) QoS channels of the distributed scheduling architecture into a single non-guaranteed-delay queue in the switch fabric. The mechanism allows to satisfy the bandwidth requirements of the GB traffic while maximizing the throughput of the BE traffic and distributes the available excess bandwidth between different types of traffic fairly. The presentation is supported by fluid stationary analysis and packet-level simulations.

A family of ASIC devices for next generation distributed packet switches with QoS support for IP and ATM

The protocol-independent (/spl pi/) family of ASIC devices, which we present in this paper, allows to build cost-effective IP routers and ATM switches capable of providing sophisticated Quality-of-Service (QoS) guarantees in the form of throughput, delay and jitter to individual flows or to aggregation of flows. The new chipset, which represents the evolution of the widely used ATLANTA chipset, comprises five devices. The devices presented considerable design and verification challenges, due to the complexity and required speed of the desired QoS functionality. To solve these challenges, we devised a number of design techniques, as well as a novel ad-hoc verification approach.

Logical Time in Distributed Software Systems

This paper presents a survey of implementation of logical time in asynchronous distributed systems. We provide an argument that justifies the use of logical time as a mechanism for detecting causal relationships between events. Further, we formally introduce the notion of a logical time system (a logical clock) and proceed to discuss the properties of the scalar, vector, and matrix clocks. Finally, we consider the modifications of the vector clock that reduce the average communication overhead while retaining the property of isomorphism.

On Implementation of Logical Time in Distributed Systems Operating over Wireless Data Networks

We address the problem of maintaining logical time in a distributed system operating over a wireless data network. In such a network a group of mobile nodes currently located in a specific area use services of a mobility service agent to communicate with each other and with the rest of the world. The graph model of the network is represented by fully-connected mesh of star-topology subgraphs. We discuss the complementary logical clocks for the wireline and wireless segment of the network and their integration into an isomorphic logical time system.

On Implementation of Logical Time in Distributed Systems Operating over a Wireless IP Network

We address the problem of maintaining logical time in a distributed system operating over a special type of a network: one whose underlying graph is represented by fully-connected mesh of star-topology subgraphs. Such a graph is generated, for example, by a wireless IP networkin which mobility service agents, interconnected by an IP backbone, provide wireless connectivity to mobile hosts currently present in the associated location areas. We discuss the complementary logical clocks for the wireline and wireless segment of the networkand their integration into an isomorphic logical time system.