Andrea Manuzzato

Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs

We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory bits controlling the different resources in the FPGA. We then study how SEU accumulation in the configuration memory impacts on the reliability of unhardened and hardened-by-design circuits. We analyze different hardening solutions comprising the use of a single voter, multiple voters, and feedback voters implemented with a commercial tool. Finally, we present an analytical model to predict the failure rate as function of the number of bit-flips in the configuration memory.

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs

Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing tuning known mitigation techniques accordingly. Radiation experiments results are presented and commented demonstrating that the proposed methodology is a viable solution to measure the transient pulses width.

Methodologies to Study Frequency-Dependent Single Event Effects Sensitivity in Flash-Based FPGAs

Flash-based FPGAs are more and more interesting for space applications because of their robustness against Single Event Upsets (SEUs) in configuration memory. However, as Single Event Effects (SEEs) are still a concern both for user memory and the configurable logic, accurate evaluations are needed to identify mitigation techniques for securing their use in space missions. In this paper the SEE sensitivity of circuits implemented in Flash-based FPGAs is evaluated with respect to the working frequency and different routing schemes. We outline different methodologies that can be used in order to characterize SEE sensitivity, using both heavy-ions radiation experiments and analytical approaches. Experimental results detail the contributions of different SEEs as a function of operating frequency and routing on a realistic circuit.

Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs

We present an experimental analysis of the sensitivity of SRAM-based FPGAs to alpha particles. We study how the different resources inside the FPGA (LUTs, MUXs, PIPs, etc. ) are affected by alpha-induced SEUs, assessing the cross section for the configuration memory cells controlling each of them. We then show two case studies, a chain of FIR filters and a series of soft microcontrollers implemented in the FPGA, measuring the rate of functional interruptions during exposure to a constant flux of alpha particles. The designs are then hardened using triplication with a single final voter, with intermediate voters, and finally including also feedback voters. The robustness of each hardening solution is discussed, analyzing the trade-off between area and fault-tolerance as a function of the number of SEUs in the configuration memory. An analytical model to predict the cross section of a given design with and without hardening solutions is finally proposed, starting from the experimental data.

Neutron Beam Testing of High Performance Computing Hardware

Microprocessor-based systems are the most common design for high-performance computing (HPC) platforms. In these systems, several thousands of microprocessors can participate in a single calculation that could take weeks or months to complete. When used in this manner, a fault in any of the microprocessors could cause the computation to crash or cause silent data corruption (SDC), i.e.~computationally incorrect results. In recent years, neutron-induced failures in HPC hardware have been observed, and researchers have started to study how neutron radiation affect microprocessor-based scientific computations. This paper presents results from an accelerated neutron test focusing on two microprocessors used in Roadrunner, the first Petaflop system.

Neutron Sensitivity of High-Speed Networks

Recently, engineers have been studying on-payload networks for fast communication paths. Using intrasystem networks as a means to connect devices together allows for a flexible payload design that does not rely on dedicated communication paths between devices. In this manner, the data flow architecture of the system can be dynamically reconfigured to allow data routes to be optimized for the application or configured to route around devices that are temporarily or permanently unavailable. To use intrasystem networks, devices will need network controllers and switches. These devices are likely to be affected by single-event effects, which could affect data communication. In this paper, we will present radiation data and performance analysis for using a Broadcom network controller in a neutron environment.

High‐Reliability Computing For The Smarter Planet

As computer automation continues to increase in our society, the need for greater radiation reliability is necessary. Already critical infrastructure is failing too frequently. In this paper, we will introduce the Cross‐Layer Reliability concept for designing more reliable computer systems.