Heather Quinn

SRAM FPGA Reliability Analysis for Harsh Radiation Environments

This paper investigates the viability of deploying SRAM-based FPGAs into harsh Earth-orbit environments. A reliability model is presented for estimating the MTTF of SRAM FPGA designs in specific orbits and orbit conditions. The model requires orbit- and condition-specific SEU rates and design-specific estimates of the probability of failure during a single scrubbing period. Probability of failure estimates are reported for several FPGA designs from both fault-injection and accelerator experiments. The model also includes a method for estimating composite mean time to failure (MTTF) that incorporates all orbit conditions over a solar cycle. Despite using pessimistic assumptions, the results from this model suggest that SRAM FPGA designs protected by TMR and scrubbing operate very reliably in a LEO orbit and surprisingly well in ¿harsh¿ orbits.

Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs

This paper discusses the limitations of single-FPGA triple-modular redundancy in the presence of multiple-bit upsets on Xilinx Virtex-II devices. This paper presents results from both fault injection and accelerated testing. From this study we have found that the configurable logic blocks routing network is vulnerable to domain crossing errors, or TMR defeats, by even 2-bit multiple-bit upsets.

Static Proton and Heavy Ion Testing of the Xilinx Virtex-5 Device

This paper presents proton and heavy ion static results for the latest Xilinx field-programmable gate arrays (FPGAs). The paper analyzes static bit cross-sections, resources, multiple-bit upsets (MBUs) and angular effects.

Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing

As of 2013, the gold standard for assessing radiation-hardness assurance (RHA) for a system, subsystem, or a component is accelerated radiation testing and/or pulsed laser testing. Fault injection tools, which include both fault simulation and emulation tools, have become more common in the last 15 years. Fault simulation tools use analytical methods for assessing RHA, whereas fault emulation uses hardware methods. Both fault simulation and emulation allow designers to augment traditional RHA techniques to determine whether circuit designs, microarchitectures, components, and application-specific integrated circuits (ASICs) meet the requirements for a particular mission. Fault simulation and emulation can provide the designers the luxury of testing on the benchtop without the time and financial constraints of accelerated radiation testing. This paper explores how to design, implement, and validate a fault simulation or emulation system. The paper ends with several case studies of currently used fault simulation and emulation systems.

Terrestrial-based radiation upsets: a cautionary tale

Problems with terrestrial-based neutron radiation from cosmic rays have become more commonplace. While the incident rate from neutron radiation is lower than space-based radiation, physics, system design and system locations have combined to make systems increasingly vulnerable to terrestrial radiation. FPGA systems are particularly sensitive to neutron radiation, as the FPGAs, microprocessors and memory are all sensitive to upsets. We are interested in reconfigurable supercomputers, which need to be highly reliable and highly available despite being very sensitive to radiation. In this paper, we estimate the error rate for FPGAs, memory, and microprocessors so that predictions for the sensitivity of the Cray XD1 reconfigurable supercomputer can be made. We also present possible mitigation methods that are appropriate for neutron radiation upset rates.

Vision for cross-layer optimization to address the dual challenges of energy and reliability

We are rapidly approaching an inflection point where the conventional target of producing perfect, identical transistors that operate without upset can no longer be maintained while continuing to reduce the energy per operation. With power requirements already limiting chip performance, continuing to demand perfect, upset-free transistors would mean the end of scaling benefits. The big challenges in device variability and reliability are driven by uncommon tails in distributions, infrequent upsets, one-size-fits-all technology requirements, and a lack of information about the context of each operation. Solutions co-designed across traditional layer boundaries in our system stack can change the game, allowing architecture and software (a) to compensate for uncommon variation, environments, and events, (b) to pass down invariants and requirements for the computation, and (c) to monitor the health of collections of devices. Cross-layer codesign provides a path to continue extracting benefits from further scaled technologies despite the fact that they may be less predictable and more variable. While some limited multi-layer mitigation strategies do exist, to move forward redefining traditional layer abstractions and developing a framework that facilitates cross-layer collaboration is necessary.

A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs

Using reconfigurable static random access memory (SRAM)-based field-programmable gate arrays (FPGAs) for space-based computation has been a very active area of research for the past decade. Because these commercially available devices are only radiation tolerant in terms of total ionizing dose and single-event latchup, these devices must be qualified for other types of single-event effects to be used in spacecraft. Furthermore, mission requirements often dictate the need to do radiation experiments on the FPGA user circuit. Because both the circuit and the circuits state are stored in memory that is susceptible to single-event upsets, both could be altered by the harsh space radiation environment. Both the circuit and the circuits state can be protected by triple-modular redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe both device-level static testing and user circuit dynamic testing, including a three-tiered methodology for testing FPGA user designs for space readiness.

Assessment of the Impact of Cosmic-Ray-Induced Neutrons on Hardware in the Roadrunner Supercomputer

Microprocessor-based systems are a common design for high-performance computing (HPC) platforms. In these systems, several thousands of microprocessors can participate in a single calculation that may take weeks or months to complete. When used in this manner, a fault in any of the microprocessors could cause the computation to crash or cause silent data corruption (SDC), i.e., computationally incorrect results that originate from an undetected fault. In recent years, neutron-induced effects in HPC hardware have been observed, and researchers have started to study how neutrons impact microprocessor-based computations. This paper presents results from an accelerated neutron-beam test focusing on two microprocessors used in Roadrunner, which is the first petaflop supercomputer. Research questions of interest include whether the application running affects neutron susceptibility and whether different replicates of the hardware under test have different susceptibilities to neutrons. Estimated failures in time for crashes and for SDC are presented for the hardware under test, for the Triblade servers used for computation in Roadrunner, and for Roadrunner.

A Method and Case Study on Identifying Physically Adjacent Multiple-Cell Upsets Using 28-nm, Interleaved and SECDED-Protected Arrays

Extracting information about MCUs from SEU data sets can be a challenge without physical layout information. Many modern static-random access memory (SRAM) components interleave memory cells to improve the robustness of error-correcting codes (ECC) that detect and correct errors in the memory array. Bit interleaving has also become popular with other components with large SRAM arrays, including field-programmable gate arrays (FPGAs). In this paper, we present a technique for extracting MCUs statistically from radiation test data. Further, we use this technique to extract MCU information from a 28-nm FPGA that uses interleaving to protect the configuration memory.

On-Orbit Results for the Xilinx Virtex-4 FPGA

This paper provides information regarding the use of the Xilinx Virtex-4 field-programmable gate array in a spacecraft deployed to low-earth orbit. The results are compared to pre-deployment accelerated and fault-injection testing.