Andreas Bertz

A novel high aspect ratio technology for MEMS fabrication using standard silicon wafers

A novel CMOS-compatible technology for the fabrication of MEMS based on standard single crystal silicon wafers is available at the Center of Microtechnologies [1]. High Aspect Ratio Microstructures (HARMs) are manufactured using a three mask level technology and dry processing throughout. The released micromechanical components consist of monocrystalline silicon without additional thin films after processing. As a result of the novel process flow the structures are surrounded by air gaps and fixed by special anchors. These Air gap Insulated Microstructures (AIM) were fabricated and tested with respect to mechanical stability, temperature dependence and electrical behavior. The low production costs and high device performance of the fabricated sensors and actuators demonstrate the ability of the technology for high volume production.

Effects of the biasing frequency on RIE of Cu in a Cl2-based discharge

The reactive ion etching of copper films is examined in several Cl2 containing gas mixtures at different discharge frequencies. Low (< 1 MHz) and high (13.56 MHz) frequency biasing was used to study the influence of the ion bombardment on the etch profile. Using the low excitation frequency anisotropic profiles have been obtained even without the formation of a thick sidewall protecting film in contrast to the high frequency discharge. Despite the enhanced ion bombardment using the low frequency discharge, the etch selectivity with respect to masking and bottom materials, respectively, is high enough for its application in multilevel metallization systems. To reduce any residues in the etch ground the addition of CF4 to the Cl2Ar mixture was found to be advantageous for low Cl2 partial pressures. Both PVD-Cu and CVD-Cu layers have been patterned with dimensions of about 1 μm.

Electrical and adhesion properties of plasma-polymerised ultra-low k dielectric films with high thermal stability

New intermetal dielectrics with dielectric constants (k) less than the dielectric constant of the conventionally used SiO2 (k=3.9) are required for the fabrication of low voltage integrated circuits due to their ability to decrease signal delay time, crosstalk and power dissipation. In this paper results of depositing and investigating CF polymers will be presented. The films were deposited in a single wafer PECVD (plasma enhanced chemical vapor deposition) equipment (Secon 251) using a mixture of C, F and H containing gases. The polymer films are stable for temperatures as high as 425°C (shrinkage <1%) maintaining a dielectric constant k even lower than 2.0 (depending on the deposition parameters and annealing processes). Furthermore, the adhesion of the CF films on top of several inorganic materials could be proved by tape test and following CMP processing. ICP patterned vias (polymer thickness: 1 μm; aspect ratio: 5) showed strong vertical profile.

Development and characterisation of a high aspect ratio vertical FET sensor for motion detection

In this paper the development, the fabrication and the experimental characterisation of a novel vertical field effect transistor (vertical FET) is presented. The vertical FET can be used for signal conversion from the mechanical to the electrical domain. This low impedance sensing technique was realized by introducing a source and drain region in opposite of a movable mass which acts as the gate. The channel resistance between drain and source is influenced by the movable mass working as a sensing unit. Theoretical calculations and practical experiments of the structure are performed. Mechanical and electrical effects over a temperature range of -40/spl deg/C to 180/spl deg/C are investigated.

Selective adhesive bonding with SU-8 for zero-level-packaging

An adhesive bonding technique for wafer-level encapsulation of high aspect ratio microstructures (HARMS) is presented. The adhesive material is spin coated on a cap wafer and structured prior to bonding. Thus sealed cavities of variable height are created in the bonding layer. SU-8 negative photoresist is used as the adhesive material in combination with miscellaneous surface materials: silicon, silicon dioxide and aluminum. The influences of the bonding process parameters - bonding pressure, bonding temperature and process time - as well as the SU-8 layer properties on the bond strength and the homogeneity of the bond have been investigated. To evaluate the process conditions the shear strength of the bond has been measured according to the ASTM standard D 1002 for adhesive bonds. Each bond interface was tested by 32 test specimens of 10 by 10 mm2 side length. With optimal process conditions shear strength of 19.2, 23.3 and 21.3 MPa have been obtained for silicon, silicon dioxide and aluminium respectively. The application of the selective adhesive bonding technique has been successfully demonstrated by encapsulating different types of single crystal silicon inertial sensors.

High throughput, high quality dry etching of copper/barrier film stacks

Dry etching of copper interconnect lines in a chlorine-based plasma has been investigated. Copper dry etching was carried out in a modified diode-type reactive ion etch (RIE) system and in an inductively coupled plasma (ICP) etch system. The ICP system offers a significant increase in copper etch rate compared with the low-efficiency RIE system while maintaining excellent pattern transfer accuracy. A number of fundamental issues in high quality and high throughput copper dry etching will be discussed. Electrical characterization of patterned copper lines with line width as small as 0.25 μm indicates low electrical resistivity and good electromigration performance.

Copper dry etching technique for ULSI interconnections

Abstract As a consequence of the well-known difficulties in reactive dry Cu patterning only a small number of processes has been published world-wide. Using a simple Cl2 based chemistry including an intense ion bombardment as an alternative approach, the formation of thick sidewall films during etching (as proposed by other groups) is not necessary. As will be shown, a copper dry etching technique for interconnections down to 0.2 μm has been developed. The line resistance of PVD- and CVD-Cu has been measured indicating a good correlation with the calculated values. Finally, first electromigration resistance measurements of PVD-Cu lines have been performed.

Mechanism studies of Cu RIE for VLSI interconnections

In this paper, an etch mechanism study of a chlorine based Cu RIE is presented. It has been generally accepted that the chlorination of Cu and the volatilization of (CuCl)/sub 3/ are essential steps during RIE of Cu in a chlorine based discharge. The exposure of Cl/sub 2/ to a Cu surface leads to a chlorinated surface layer whose thickness increases with exposure. Based on these results we have investigated the chlorination of Cu in a reactive plasma at elevated temperature. In order to minimize isotropic etching or chlorine residues in the remaining Cu film it is necessary to reduce the thickness of the chlorinated film. One way to do this is to lower the Cl/sub 2/ partial pressure. The influence of the Cl/sub 2/ partial pressure on the Cu chlorination is discussed. AES surface measurements at the etch bottom and the Cu sidewall after RIE interruption have been carried out showing only a very thin chlorinated surface layer.

Thin Filmencapsulation of microstructures using Sacrificial CF-Polymer

This paper reports on a new method for thin film encapsulation of microelectromechanical systems (MEMS) using plasma enhanced chemical vapor deposited (PECVD) fluorocarbon polymer as sacrificial material and a stress optimized SiO/SiN capping layer. This technique is applicable for a wide range of MEMS technologies - high aspect ratio as well as surface microstructures - it saves die area and enables standard packaging processes such as dicing and pick and place. Beside of the fabrication technology, this paper presents results of a finite element analysis (FEA) regarding the deflection and mechanical stress due to a pressure difference between the cavity and the ambient. The results of the FEA were verified by interferometric measurements on fabricated test structures.

A single-crystal Si-resonator with on-chip readout amplifier in standard CMOS

The monolithic integration of electronic circuits in standard CMOS technology with high aspect ratio micromechanical structures based on single-crystal silicon is presented. For this technology neither silicon on insulator (SOI) wafers nor wet processes are required. A resonator device is chosen for technology demonstration. The effect of micromachining on parameters of CMOS transistors is detected and the usefulness of a final annealing step is confirmed. A novel electronic circuit design allows signal processing, even for low resonator signal levels and strong parasitic effects.