Andreas C. Döring

Robust header compression (ROHC) in next-generation network processors

Robust Header Compression (ROHC) provides for more efficient use of radio links for wireless communication in a packet switched network. Due to its potential advantages in the wireless access area and the proliferation of network processors in access infrastructure, there exists a need to understand the resource requirements and architectural implications of implementing ROHC in this environment. We present an analysis of the primary functional blocks of ROHC and extract the architectural implications on next-generation network processor design for wireless access. The discussion focuses on memory space and bandwidth dimensioning as well as processing resource budgets. We conclude with an examination of resource consumption and potential performance gains achievable by offloading computationally intensive ROHC functions to application specific hardware assists. We explore the design tradeoffs for hardware assists in the form of reconfigurable hardware, Application-Specific Instruction-set Processors (ASIPs), and Application-Specific Integrated Circuits (ASICs).

Cooperative software multithreading to enhance utilization of embedded processors for network applications

Multithreading is an efficient way to improve efficiency of processor cores in embedded products for networking infrastructures. To make such improvements also accessible to processor cores without hardware support for multithreading, we present a concept for efficient software multithreading through compiler post-pass optimization of the application code. Our approach aims at reducing the overhead for cooperative multithreading context switches at compile time by using standard compiler techniques such as context-insensitive analysis. Additionally, register usage is rearranged to reduce the amount of context-switch code by exploiting multiple-load/store instructions. Performance model analysis encourages the use of software multithreading to improve processor utilization by showing the benefit of our approach. We present results obtained by an implementation for the PowerPC ISA (Instruction Set Architecture) using the code of a real network application (iSCSI). We were able to reduce the expected run-time of a context switch to as little as 38% of the original.

A flexible approach for a fault-tolerant router

Cluster systems gain more and more importance as a platform for parallel computing. In this area the power of the system is strongly coupled with the performance of the network, which has to provide high bandwidth and low latency. Besides these performance aspects fault-tolerance within the network is very important. This paper shows how to build a flexible and fault-tolerant router, the main building part of a network. In addition the overhead for the execution of fault-tolerant routing algorithms is examined.

Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory

Multidimensional arrays are among the most common data types. Their use in configurable hardware requires the injective translation of the index tuple into a memory address. This problem is considered in the paper, searching for a balance between speed and waste of memory. The basic idea is to divide one of the index ranges such that one part is a power of two. In this way the indices can be concatenated with fewer loss. To combine both resulting parts into one memory, several techniques are used. The integration of the proposed method into libraries and tools allows efficient description of algorithms on a higher abstraction level.

Parallel Processing in Network Processor Architectures (Parallelverarbeitung in Netzwerkprozessorarchitekturen)

Summury Parallel processing is well established in high-performance computing. Currently, network processors as new emerging, special-purpose processors are targeted at the exploitation of parallelism to meet the requirements in data-plane processing with wire-speed. The achievable level of parallelism is determined by decisions in the architecture design and by the characteristics of the data-plane applications executed. We discuss two basic approaches in parallel processing, namely pipelining and concurrency, which establish basic models for parallel network processor organization. The features and constraints of these models are studied. Using this background some existing network processor architectures are reviewed and characterized regarding their potential in parallel data-plane processing.

Implementation of Finite Lattices in VLSI for Fault-State Encoding in High-Speed Networks

In this paper the propagation of information about fault states and its implementation in high-speed networks is discussed. The algebraic concept of a lattice (partial ordered set with supremum and infimum) is used to describe the necessary operation. It turns out that popular algorithms can be handled this way. Using the properties of lattices efficient implementation options can be found.

Programming and Implementation of Reconfigurable Routers

Clusters made from standard PCs or workstations interconnected by a high-speed network form a high-performance parallel computer. High-speed networks consist of routers switching the data via several wire segments. In order to allow flexible use of the network the routers have to be reconfigurable. Such a router is described as an application of reconfiguration techniques and standard devices like FPGAs. The presented approach is based on the use of sets of rules to describe the routers behavior in a flexible manner. The rule set is translated to generate configuration data for the hardware.

Analysis of network topologies and fault-tolerant routing algorithms using binary decision diagrams

In the past a plethora of network topologies together with fault-tolerant routing algorithms have been proposed. Some properties have been analyzed analytically or by simulation. In most cases only some properties can be derived. There is renewed interest in the topic for application as networks-on-chip. The availability of higher computing performance and libraries for manipulating binary decision diagrams allows the complete analysis in an automated fashion. The approach is presented in this paper together with some insights on strategies to keep the computational effort reasonable when scaling the network size.

Impact of coprocessors on a multithreaded processor design using prioritized threads

Recently, multithreading became a standard technique to improve the processor utilization and system performance. Hardware support is provided for coarse-grained as well as simultaneous multithreading. In particular, embedded devices combine processor cores and varying sets of coprocessors to fulfill the requirements of their dedicated application field. In this paper, a simultaneous multithreaded processor is investigated that applies dynamic priorities for each thread on the instruction level. By means of a synchronization coprocessor, priorities of threads are dynamically adapted when other threads have to wait for a given thread. Based on simulations of a network-processing workload, two strategies of dynamic priority adaptation are evaluated and compared with static prioritization. As a result, performance gain can be shown.

Low-Level SCI Protocols and Their Application to Flexible Switches

The purpose of SCI is to provide a fast interconnection technology for up to thousands of components. This chapter discusses several aspects of the protocols used in SCI, especially regarding requirements and possibilities for their implementation in hardware. One motivation behind the SCI standardization effort was to enable SCI as interconnect for peripherals or memory subsystems. Therefore, we discuss how the protocols can be implemented efficiently and in a small chip area.