Patricia M. Sagmeister

Early analysis tools for system-on-a-chip design

The paper describes the need for early analysis tools to enable developers of todays system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.

The cache and memory subsystems of the IBM POWER8 processor

In this paper, we describe the IBM POWER8™ cache, interconnect, memory, and input/output subsystems, collectively referred to as the “nest.” This paper focuses on the enhancements made to the nest to achieve balanced and scalable designs, ranging from small 12-core single-socket systems, up to large 16-processor-socket, 192-core enterprise rack servers. A key aspect of the design has been increasing the end-to-end data and coherence bandwidth of the system, now featuring more than twice the bandwidth of the POWER7® processor. The paper describes the new memory-buffer chip, called Centaur, providing up to 128 MB of eDRAM (embedded dynamic random-access memory) buffer cache per processor, along with an improved DRAM (dynamic random-access memory) scheduler with support for prefetch and write optimizations, providing industry-leading memory bandwidth combined with low memory latency. It also describes new coherence-transport enhancements and the transition to directly integrated PCIe® (PCI Express®) support, as well as additions to the cache subsystem to support higher levels of virtualization and scalability including snoop filtering and cache sharing.

Design optimization of a highly parallel InfiniBand host channel adapter

Network processors use highly parallel architectures to improve performance and reach multi-gigabit line-speeds. In this paper, we emulate a pipeline in a highly parallel non-programmable industrial InfiniBand Host Channel Adapter to make a performance and bottleneck analysis and, at the same time, explore the potential of a pipelined architecture. Therefore, starting from the original Host Channel Adapter model with multiple send- and receive-side packet-processing units, we compare its performance capabilities with that of a pipelined design by introducing a central arbiter synchronizing the state machines of the different packet-processing instances to achieve a pipelined behavior. We show that the pipelined model achieves a performance comparable to that of the parallel design in most of our micro-benchmarks, making it a valid option for next-generation high-speed adapters. At the same time, our approach enables a deeper analysis of the original architecture and a better understanding of the actual processing requirements, and therefore offers valuable insights for future designs.