Andreas Emeretlis

A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms

The development of efficient methods for mapping applications on heterogeneous multicore platforms is a key issue in the field of embedded systems. In this article, a novel approach based on the Logic-Based Benders decomposition principle is introduced for mapping complex applications on these platforms, aiming at optimizing their execution time. To provide optimal solutions for this problem in a short time, a new hybrid model that combines Integer Linear Programming (ILP) and Constraint Programming (CP) models is introduced. Also, to reduce the complexity of the model and its solution time, a set of novel techniques for generating additional constraints called Benders cuts is proposed. An extensive set of experiments has been performed in which synthetic applications described by Directed Acyclic Graphs (DAGs) were mapped to a number of heterogeneous multicore platforms. Moreover, experiments with DAGs that correspond to two real-life applications have also been performed. Based on the experimental results, it is proven that the proposed approach outperforms the pure ILP model in terms of the solution time and quality of the solution. Specifically, the proposed approach is able to find an optimal solution within a time limit of 2 hours in the vast majority of performed experiments, while the pure ILP model fails. Also, for the cases where both methods fail to find an optimal solution within the time limit, the solution of the proposed approach is systematically better than the solution of the ILP model.

High-performance FPGA implementations of volterra DFEs for optical fiber systems

Low-complexity Volterra Decision Feedback Equalizers (VDFEs) for optical fiber links are proposed. By properly discarding large blocks of coefficients in the feedforward and feedback sections of the equalizer, a significant complexity reduction is achieved without affecting its efficiency. Moreover, suitable architectures and high-performance FPGA implementations are provided. It is demonstrated that the efficiency of the proposed VDFEs in terms of BER is similar to the counterpart full-size VDFEs for links of the same length, while, they demand 50% less arithmetic resources. Also, the proposed DFEs meet the desired 10 Gb/s rate and in certain cases achieve rates of 17 Gb/s and 25 Gb/s.

40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links

A low complexity MIMO Volterra Decision Feedback Equalizers (VDFE) for optical transmission systems employing NRZ-DQPSK signalling is proposed. Based on a comparative study performed by means of simulations, it is proved that the proposed equalizers maintain the required efficiency in terms of BER, achieving significant reduction in terms of complexity. Also, suitable architectures for high-speed FPGA implementations are presented. A 8-input 2-output low complexity VDFE involving three taps feed-forward filtering and two taps backward filtering was implemented on a single state-of-the-art FPGA. The target rate of 40 Gb/s is achieved by applying extensive pipelining and parallelism and fully exploiting specific FPGA features.

FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links

In this paper, an FPGA implementation of a Multi Input Multi Output (MIMO) Decision Feedback equalizer (DFE) is proposed, for the electronic compensation of the impairments in 40Gb/s Intensity Modulated Direct Detection (IM/DD) optical communication links employing NRZ DQPSK signaling. The proposed equalizer is used for the electronic compensation the residual Chromatic Dispersion (CD) along the installed optically compensated optical paths. The required processing rate is achieved by applying intensive pipelining and parallelism in the original architecture of the equalizer. At the given processing rate, a 8-input 2-output DFE involving three taps feedforward filtering and two taps backward filtering is implemented on a single, cutting edge technology, Xilinx FPGA device.

A hybrid approach for mapping and scheduling on heterogeneous multicore systems

A hybrid approach for mapping applications represented as Directed Acyclic Graphs (DAGs) is introduced in this work. It combines the Benders decomposition principle, which integrates Integer Linear and Constraint Programming (ILP and CP) methods, with a pure ILP model to find optimal solutions. The cuts that are generated during the iterative Benders solution process are later exploited by the ILP solver to prune the remaining search space. The proposed model succeeds to provide the optimal solution in cases where either method alone fails to do so, while it also reduces the total solution time.

Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion

Efficient mapping of DAGs on heterogeneous multicore platforms is a key component for modern embedded applications. An approach based on the Benders decomposition principle that uses a heuristic pre-solver and Integer Linear and Constraint Programming methods to find proven-optimal solutions is introduced. We present multiple cuts generation schemes, that improve the performance of the solution process, and extensive experimental results, that show significant speedups compared to the pure ILP-based method.

A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures

Directed Acyclic Task Graphs serve as typical kernel representation for embedded applications. Modern embedded multicore architectures raise new challenges for efficient mapping and scheduling of task DAGs providing a large number of heterogeneous resources. In this paper, a hybrid Integer Linear Programming - Constraint Programming method that uses the Benders decomposition is used to find proven optimal solutions. The proposed method is augmented with cuts generation schemes for accelerating the solution process. Experimental results show that the proposed method systematically outperforms an ILP-based solution method.

FPGA Implementations for Volterra DFEs

In this paper a high-throughput FPGA implementation of a Volterra-based Decision Feedback Equalizer (DFE) is presented for first time. The DFE is a popular scheme, and its performance is a critical issue in high-speed communication systems. To overcome the throughput limitation due to the feedback loop, two multiplexer-based architectures were developed and compared. The introduced architectures were implemented on two Xilinx FPGAs, exploiting the specific features of these devices. Based on the experimental results, it is proved that the introduced designs achieve high throughput (10Gb/s), showing that the FPGAs are a suitable option for high-speed systems (e.g. optical communication systems).

Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming

The proper mapping of an application on a multi-core platform and the scheduling of its tasks are key elements to achieve the maximum performance. In this article, a novel hybrid approach based on integrating the Logic-Based Benders Decomposition (LBBD) principle with a pure Integer Linear Programming (ILP) model is introduced for mapping applications described by Directed Acyclic Graphs (DAGs) on platforms consisting of heterogeneous cores. The LBBD approach combines two optimization techniques with complementary strengths, namely ILP and Constraint Programming (CP), and is employed as a cut generation scheme. The generated constraints are utilized by the ILP model to cut possible assignment combinations aiming at improving the solution or proving the optimality of the best-found one. The introduced approach was applied both on synthetic DAGs and on DAGs derived from real applications. Through the proposed approach, many problems were optimally solved that could not be solved by any of the above methods (ILP, LBBD) alone within a time limit of 2 hours, while the overall solution time was also significantly decreased. Specifically, the hybrid method exhibited speedups equal to 4.2× for the synthetic instances and 10× for the real-application DAGs over the LBBD approach and two orders of magnitude over the ILP model.