Andreas Loos

An Organic Computing architecture for visual microprocessors based on Marching Pixels

The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distributed and emergent functionality exploited for detection of objects and their center points given in binary images. Future real-time embedded systems used in industrial image processing have to provide reply times in the range of milliseconds. It is impossible to meet such strict requirements for megapixel resolutions with serial processing schemes in particular if multiple given objects have to be detected. Even classical parallel techniques like SIMD or MIMD approaches are not sufficient due to their dependency on more or less central control structures. To achieve more flexibility, unlimited scalability and higher performance parallel emergent architectures are necessary. We present such an approach, denoted as marching pixels, for future digital visual microprocessors. Marching pixels work similar to artificial ants. They are crawling as hardware agents within a pixel field, e.g. to identify and to detect center points of an arbitrary number of objects given in an image. We present an emergent marching pixel algorithm for the processing of arbitrary concave objects and its mapping onto real hardware. Based on synthesis results for FPGAs and ASICs we discuss the possibilities of digital organic computing approaches for visual microprocessors for future smart high-speed camera systems.

ASIC Architecture to Determine Object Centroids from Gray-Scale Images Using Marching Pixels

The paper presents a SIMD architecture to determine centroids of objects in binary and gray-scale images applying the Marching Pixels paradigm. The introduced algorithm has emergent and self- organizing properties. A short mathematic derivation of the system behavior is given. We show that a behavior describing the computation of object centroids in gray-scale images is easily derived from those of the binary case. After the architecture of a single calculation unit has been described we address a hierarchical three-step design strategy to generate the full ASIC layout, which is able to analyze binary images with a resolution of 64×64 pixels. Finally the latencies to determine the object centroids are compared with those of a software solution running on a common medium performance DSP platform.

Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips

We present results of an investigation concerning the appropriateness of different parallel SIMD architectures based on reconfigurable approaches for an integration in an one-chip high speed smart CMOS camera. The processing elements (PEs) of the architecture combine parallel analogue optical signal detection and parallel digital signal processing to meet real-time requirements. However, the parallel architecture puts some constraints on the PE architecture. To achieve reasonable pixel resolutions and fill factors the PE area has to be as low as possible. Additionally a single PE must also offer sufficient functional flexibility. We show by a logic synthesis that reconfigurable architectures based on morphological operations are the best solution to fulfill these constraints. Furthermore we present simulation results of a first test chip which we designed as an OPTO-ASIC with a simple SIMD chip architecture.

Dynamically Programmable Image Processor for Compact Vision Systems

We present a fine-grain parallel processor chip which can be embedded in very compact machine vision systems, e.g. in 3d stacked die assemblies. Smart and fast vision systems are frequently required in industrial environments to automatically detect and inspect objects, e.g. on an assembly line. The chip die has a size of 25 mm² and is manufactured using a 0.18 um CMOS technology. The chip processes binary images with a maximum resolution of 320x240 pixels (QVGA) supplied by a separate closely-linked image sensor array. It is possible to process an image in multiple cycles where a set of morphological operations can be subsequently combined depending on the image processing problem. In addition the chip is able to compute more complex user-defined programs, e.g. to skeletonize images. The output data can be a preprocessed image or projection representations in horizontal, vertical and diagonal direction, which reduces the data amount. Therefore a faster image post-processing is supported, e.g. to calculate objects momenta. The chip is driven by a 40 MHz clock. As result a base morphological operation including image in/output needs only 250 us. For even faster data in/output a ROI (region of interest) can be defined. Two standardized interfaces (JTAG, SPI) allow to parameterize as well as to program the circuit.

A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems

Due to the increasing needs of always faster automation technology in the field of industrial fabrication the common methods of machine vision meet their limits. The reasons are the widely used serial computation and transmission of data streams on the base of strict spatially separated data capturing by an image sensor and data processing, e.g. by a coupled DSP. To meet serious real time requirements many discrete high speed components are used which often causes high costs. In contrast we propose a 3D architecture based on stacked chip dies. In order to find a trade-off between speed and required chip area we present a space-time multiplex architecture, i.e. clusters of pixels are processed time-serially by one processor and several clusters are processed by a multi-core processor. Our architecture allows the successive computation of basic low-level image processing operations. We determined an optimal number of serially processed pixels between 16 and 32 in a cluster for a resolution of 256times256 pixels. Furthermore we found out that the most efficient way is to process a line based cluster