Lutz Hoppe

Optical interconnects for neural and reconfigurable VLSI architectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits.

Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips

We present results of an investigation concerning the appropriateness of different parallel SIMD architectures based on reconfigurable approaches for an integration in an one-chip high speed smart CMOS camera. The processing elements (PEs) of the architecture combine parallel analogue optical signal detection and parallel digital signal processing to meet real-time requirements. However, the parallel architecture puts some constraints on the PE architecture. To achieve reasonable pixel resolutions and fill factors the PE area has to be as low as possible. Additionally a single PE must also offer sufficient functional flexibility. We show by a logic synthesis that reconfigurable architectures based on morphological operations are the best solution to fulfill these constraints. Furthermore we present simulation results of a first test chip which we designed as an OPTO-ASIC with a simple SIMD chip architecture.

Realization of regular fiber bundles with defined pitch

We show a technology to overcome a known bottleneck in the communication between processor and memory or, especially in multiprocessor systems, among the processors themselves. The solution is communication with the help of fiber bundles with defined pitch. The disadvantages of microstructures based on poly-methyl-meth-acrylate are described. Attractive alternatives based on silicon for precisely structured elements are explained. A practical example of a fiber array is visualized.