Andreas Mai

A 0.13

A 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented. This technology features high-speed HBTs (f<inf>T</inf>=240 GHz, f<inf>max</inf>=330 GHz, BV<inf>CEO</inf>=1.7 V) along with high-voltage HBTs (f<inf>T</inf>=50 GHz, f<inf>max</inf>=130 GHz, BV<inf>CEO</inf>=3.7 V) integrated in a dual-gate, triple-well RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators for frequencies above 200 GHz are demonstrated.

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A novel waveguide-coupled germanium p-i-n photodiode is demonstrated which combines high responsivity with very high -3 dB bandwidth at a medium dark current. Bandwidth values are 40 GHz at zero bias and more than 70 GHz at -1 V. Responsivity at 1.55 µm wavelength ranges from 0.84 A/W at zero bias to 1 A/W at -1 V. Room temperature dark current density at -1 V is about 1 A/cm2. The high responsivity mainly results from the use of a new, low-loss contact scheme, which moreover also reduces the negative effect of photo carrier diffusion on bandwidth.

SiGe BiCMOS Technology Featuring f

This work reports on the integration of n-type lateral-drain-extended MOS transistors (LDMOS) in a 0.13 µm SiGe BiCMOS technology. The transistors are realized with no additional process steps using the core dual-gate-oxide CMOS flow only. LDMOS drift regions are formed by compensating lightly-doped drain (LDD) implantations of NMOS and PMOS transistors of the baseline process. Stable operation with less than 10% parameter variations in 10 years is achieved up to operating voltages V DD,max of 10V for devices with breakdown voltages BV DSS = 30V and on-resistances R ON = 7.3Ωmm. Devices for different operating voltages V DD,max are realized by layout variations. Devices with V DD,max = 6V demonstrate breakdown voltages BV DSS = 25V, on-resistances R ON = 4.9Ωmm, and peak transit frequencies f T = 32 GHz.

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In this work different SiGe-BiCMOS based technology platforms for mm-wave and radar applications are presented. Based on the evolution of IHP BiCMOS technologies the performance improvement for SiGe-heterojunction bipolar transistor (HBT) in the past decades in comparison to scaled RF-CMOS technologies is shown. We depict that an increase of the processing effort of only 35% deliver a SiGe-HBT device performance improvement of >170% compared to IHPs first high-speed HBT generation. Moreover the co-integration of new modules with the SiGe-BiCMOS baseline technology is reviewed. The monolithic integration of an additional RF-MEMS switch module is shown and we discuss different packaging approaches for the integrated device. Furthermore a SiGe-BiCMOS/InP-bipolar heterogeneous integration platform is presented. All shown technologies had proven their usefulness for radar applications and different examples from F-band up to the 240 GHz range are reviewed.

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In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication steps, only a low-temperature fusion bonding process is applied and the integration concept is realized without adding an additional mask to the established BiCMOS via-middle TSV technology. As a result, the developed technique is very promising to realize different dimensions of TSVs on the same substrate for future smart system applications.

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In this work, an electromagnetic (EM) model and a small-signal (lumped-element) model of a wafer-level encapsulated (WLE) radio frequency microelectromechanical systems (RF-MEMS) switch is presented. The EM model of the WLE RF-MEMS switch is developed to estimate its RF performance. After the fabrication of the switch, the EM model is used to get accurate S-parameter simulation results. Alternative to the EM model, a small-signal model of the fabricated WLE RF-MEMS switch is developed. The developed model is integrated into a 0.13 µm SiGe BiCMOS process technology design kit for fast simulations and to predict the RF performance of the switch from a pure electrical point of view. The 0.13 µm SiGe BiCMOS embedded WLE RF-MEMS shows beyond state-of-the-art measured RF performances in D-band (110–170 GHz) and provides a high capacitance C on /C off ratio of 11.1. The results of the both EM model and small-signal model of the switch are in very good agreement with the S-parameter measurements in D-band. The measured maximum isolation of the WLE RF-MEMS switch is 51.6 dB at 142.8 GHz with an insertion loss of 0.65 dB.

of 240/330 GHz and Gate Delays Below 3 ps

Schottky barrier diodes (SBD) were integrated in a 0.25 μm SiGe BiCMOS technology. The SBDs were realized without additional process steps using the titanium silicide (TiSi) phase of the standard contact formation for the anode Schottky barrier. We observe a specific parameter degradation after reverse anode voltage operation. Different parameters as series resistance Rs, forward and leakage currents (IA, Ir) and design parameters like anode area, contact edge lengths and corners were evaluated in order to decrease this degradation. The on-resistance Ron and capacitance Coff were extracted by s-parameter measurements and show an obvious decreased degradation. Finally maximum reverse operating voltages for a ten year life time and a maximum change of 10% for critical parameters were extrapolated for the worst operation conditions.

High bandwidth, high responsivity waveguide-coupled germanium p-i-n photodiode

This paper proposes a hybrid-waveguide ring resonator for on-chip biochemical sensing. Consisting of a low-loss strip-waveguide and a highly sensitive slot-waveguide integrated in a silicon photonic platform, it combines advantages of both waveguide types. In this way, it provides the unique feature to increase the sensitivity while maintaining low optical losses. Thus, this resonator structure may represent a promising alternative approach for future integrated biochemical sensing applications. This is suggested by a theoretical analysis, involving numerical simulation of the hybrid-waveguide ring resonator and an optimization of the slot-waveguide structure with regard to light-analyte-interaction. It is demonstrated that the hybrid-waveguide concept may overcome limitations in terms of overall resonator sensitivity, which is described by a figure of merit, connecting the optical losses with the resonator sensitivity.

Drain-extended MOS transistors capable for operation at 10V and at radio frequencies

Complementary lateral-drain-extended MOS transistors (CLDMOS) were integrated in a 0.13 μm SiGe BiCMOS technology. The LDMOS devices were realized in the dual-gate-oxide CMOS process without additional process steps. Drift regions were formed by the lightly-doped drain (LDD) implantations of 3.3V NMOS and PMOS transistors of the baseline process. The NLDMOS transistors use a combination of n-LDD and p-LDD to form the low-doped drift region whereas the PLDMOS drift region consists of the p-LDD implantation. Stable operation with less than 10% parameter variation in 10 years was achieved up to voltages of 6 V and 10 V for complementary LDMOS devices with different layouts. Peak transit frequencies fT of 14.5 GHz and 9 GHz were demonstrated for PLDMOS transistors with Vdd,max of -6 V and -10V, respectively.

SiGe-BiCMOS based technology platforms for mm-wave and radar applications

In this paper, wafer level transfer of graphene on to a dielectric substrate is demonstrated based on SiO2-SiO2 fusion bonding and de-bonding processes. The developed technique allows to transfer graphene on 200 mm wafer without any contamination; thus CMOS compatible. The experimental data verifies the successful transfer of the graphene on to another substrate with high quality and a yield value of 98% with average 3.5 kΩ/□ sheet resistance. To the best of authors knowledge, it is the first time demonstration of the graphene transfer based on SiO2-SiO2 fusion bonding and de-bonding process on 200 mm wafer level which would allow a complete integration of graphene material into a CMOS line and opens the way for new devices based on graphene material.