Matthias Wietstruck

Robustness and reliability of BiCMOS embedded RF-MEMS switch

Robustness and reliability of an embedded RF-MEMS switch are analyzed. Changes of key switch parameters, such as COFF, CON, and pull-in voltage, with the ambient temperature are investigated in the range of −30°C to 150°C. The biggest temperature effect, a decrease by a factor of 2 between −30°C and 150°C, is observed for COFF, while CON weakly increases by only about 6% in this temperature range. For the pull-in voltage, practically no T-effect is observed. The power handling performance is also analyzed. A DC self-actuation voltage of 20V was estimated. To hold the membrane in down position, an 1.2V DC voltage drop or 15dBm RF power was found to be necessary. Finally, a new reliability test was applied, using Laser-Doppler (LD) Vibrometry technique to analyze the change in the switch dynamic behavior after billion times of operation. The measurement results show that this behavior hardly changes for up to 50 billion times operation.

Packaged BiCMOS embedded RF-MEMS switches with integrated inductive loads

This paper presents packaged BiCMOS embedded RF-MEMS switches with integrated inductive loads for frequency tuning at mm-wave frequencies. The developed technique provides easy optimization to maximize the RF performance at the desired frequency without having an effect on the switch mechanics. Insertion loss less than 0.25 dB and isolation better than 20 dB are achieved from 30 to 100 GHz. A glass cap with a silicon frame is used to package the switch. Single-pole-double-throw (SPDT) switches and a 24 – 77 GHz reconfigurable LNA is also demonstrated as a first time implementation of single chip BiCMOS reconfigurable circuit at such high frequencies.

BiCMOS integrated microfluidic platform for Bio-MEMS applications

In this paper, a fully BiCMOS integrated microfluidic platform for bio-MEMS applications is demonstrated. The novel integration process flow provides very flexible size of micro-channels in BiCMOS chip and brings the fluid very close to the sensors. The platform is demonstrated with BiCMOS integrated 120 GHz dielectric sensor and the changes of the dielectric constant of different fluids in the channel are successfully detected. The high reproducibility, small size, high throughput and low-cost process make the presented BiCMOS integrated microfluidic channel technology as a key platform for bio-MEMS and THz-sensing applications.

Single-chip transmit-receive module with a fully integrated differential RF-MEMS antenna switch and a high-voltage generator for F-band radars

A single-chip solution for short-range F-band radar systems is presented. It is based on a Transmit-Receive (TR) module realized in a 130 nm BiCMOS process, with a fully integrated chain of Gilbert-cell frequency multipliers generating the required F-band carrier for both transmit and receive paths, a differential Single-Pole-Double-Throw (SPDT) switch that relies on novel differential RF Micro-Electro-Mechanical (RF-MEMS) switches and a High-Voltage (HV) generator providing the required charging and discharging 50 V signals for the RF-MEMS switches. Thanks to a dedicated compensation strategy, the radar module can be packaged using low-cost techniques and wire-bonded to an off-chip antenna without compromising the performance in the band of interest. To boost the link budget by 30 dB, dielectric lenses are used. Full functionality of the realized TR module has been experimentally confirmed, and characterizations of the SPDT switch components, such as RF-MEMS switch and balanced transmission lines were completed.

Capping technologies for wafer level MEMS packaging based on permanent and temporary wafer bonding

This paper describes techniques for the miniaturized, low-cost wafer level chip-scale packaging of MEMS based system in packages (SiPs). The approaches comprise permanent bonding of cap structures using adhesives or solder onto a passive or active silicon wafer which is populated with MEMS components or which is itself a MEMS wafer. The paper addresses different options for manufacturing of lid or cap structures and their subsequent bonding to the partner wafer. Different technologies like bonding of full area cap wafers as well as partial capping approaches based on reconfigured cap structures on a help wafer or cap structures created on a compound wafer are presented. Examples like the selective capping process for RF-MEMS switches are discussed in detail. All processes were performed at 200 mm wafer scale.

Accurate Depth Control of Through-Silicon Vias by Substrate Integrated Etch Stop Layers

In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication steps, only a low-temperature fusion bonding process is applied and the integration concept is realized without adding an additional mask to the established BiCMOS via-middle TSV technology. As a result, the developed technique is very promising to realize different dimensions of TSVs on the same substrate for future smart system applications.

Electromagnetic and small-signal modeling of an encapsulated RF-MEMS switch for D-band applications

In this work, an electromagnetic (EM) model and a small-signal (lumped-element) model of a wafer-level encapsulated (WLE) radio frequency microelectromechanical systems (RF-MEMS) switch is presented. The EM model of the WLE RF-MEMS switch is developed to estimate its RF performance. After the fabrication of the switch, the EM model is used to get accurate S-parameter simulation results. Alternative to the EM model, a small-signal model of the fabricated WLE RF-MEMS switch is developed. The developed model is integrated into a 0.13 µm SiGe BiCMOS process technology design kit for fast simulations and to predict the RF performance of the switch from a pure electrical point of view. The 0.13 µm SiGe BiCMOS embedded WLE RF-MEMS shows beyond state-of-the-art measured RF performances in D-band (110–170 GHz) and provides a high capacitance C on /C off ratio of 11.1. The results of the both EM model and small-signal model of the switch are in very good agreement with the S-parameter measurements in D-band. The measured maximum isolation of the WLE RF-MEMS switch is 51.6 dB at 142.8 GHz with an insertion loss of 0.65 dB.

Estimation of RF performance from LF measurements: Towards the design for reliability in RF-MEMS

Abstract This paper presents a method which allows the prediction of the RF performance of capacitive RF-MEMS by measuring the UP and DOWN state capacitances. The method is based on the combined use of a very accurate lumped element equivalent circuit model and wafer level measurements of the capacitances in two different states. This approach allows very fast monitoring of the complete RF performance in the entire band, at the cost of a simple (LF) capacitance measurements and an equivalent circuit model extraction. The results presented here demonstrate the efficiency of this technique in tracking or predicting deviation due to manufacturing process dispersions or other device features difficult to account for experimentally.

Experiments on MEMS Integration in 0.25 μm CMOS Process

In this paper, we share our practical experience gained during the development of CMOS-MEMS (Complementary Metal-Oxide Semiconductor Micro Electro Mechanical Systems) devices in IHP SG25 technology. The experimental prototyping process is illustrated with examples of three CMOS-MEMS chips and starts from rough process exploration and characterization, followed by the definition of the useful MEMS design space to finally reach CMOS-MEMS devices with inertial mass up to 4.3 μg and resonance frequency down to 4.35 kHz. Furthermore, the presented design techniques help to avoid several structural and reliability issues such as layer delamination, device stiction, passivation fracture or device cracking due to stress.

I-line stepper based overlay evaluation method for wafer bonding applications

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP’s standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.