Andreas Ripp

Robust Analog Design for Automotive Applications by Design Centering With Safe Operating Areas

The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage Vth, which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable, analysis and optimization of their sensitivity to variations in model parameters is important. Furthermore, constraints on the operating regions and voltage differences of transistors are used in order to keep operating points stable over a large temperature range. In this work, using three circuits for automotive applications and current process development kits (PDK), we show how design centering software can be used to consider both sensitivity reduction towards model parameter variation and constraints to control safe operating areas (SOA).

DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design

The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now

Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas

circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices

Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)

The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage V th, which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable, analysis and optimization of their sensitivity to variations in model parameters is important. Furthermore, constraints on the operating regions and voltage differences of transistors are used in order to keep operating points stable over a large temperature range. In this work, using two circuits for automotive applications and current process development kits (PDK), we show how design centering software can be used to consider both sensitivity reduction towards model parameter variation and constraints to control safe operating areas (SOA). Beyond that a comparison of the constraint matrix method with two established methods of SOA checking is done.

Yield optimization for low power current controlled current conveyor

Process variability are getting worse with the scaled technologies especially below 90nm, therefore for the reliable fabrication outcome, the effect of both the local and global process variability should be taken into account. In this paper, verification, sizing and design centering/yield optimization for the robust second generation current controlled current conveyor (CCCII+) and CCCII+ based band pass filter for low power without degrading other performances values have been presented. Current conveyors (CC) based applications are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net lists of CCCII+ and band pass filter circuits have been simulated in Eldo using the 65nm CMOS mixed signal low-K TSMC process development kit (PDK) with 1.2V, low-Vt devices with statistical models. All analysis, sizing and optimization have been performed using the WiCkeD^T^M tool at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit.

Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell

Due to increasing CMOS process variability, optimization for yield has become one of the crucial tasks in Integrated Circuit (IC) design especially in analog IC design. This variability is getting worse with the continuous scaling of device dimensions and therefore degrades the IC fabrication outcome. This paper presents the yield optimization for low power second generation dual output current controlled current conveyor (DOCCCII). Current conveyors (CC) are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net list of given DOCCCII circuit has been simulated in Eldo using 65nm CMOS mixed signal Low-K IMD TSMC process development kit (PDK) with ±0.6V, low-Vt devices with statistical models. All verification, sizing and optimization analysis have been performed using the commercially available WiCkeD toolset from MunEDA at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit.

Systematic analysis & optimization of analog/mixed-signal circuits balancing accuracy and design time

Aging phenomena, on top of process variations along with temperature and supply voltage variations, translate into complex degradation effects on the required performance and yield of nanoscale circuits. The proposed paper focuses on the development of mathematically optimal circuit sizing for yield maximization on the case study of a CMOS full adder circuit. The final cell design is robust against NBTI aging effects, impact of statistical (global and mismatch) and operating variation of temperature and supply voltage. Monte Carlo analysis has been carried out to verify the estimated yields. The demonstrated technique can be extended to a library of optimally designed digital cells.

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design

In this paper we will demonstrate the benefits of systematic circuit analysis and optimization applied at different abstraction levels of a typical analog and mixed-signal design to address market requirements and technical challenges of nanometer technology nodes. The paper emphasizes the systematic approach using automated analysis and optimization technology in comparison with the still widely spread manual analog design approach led by designers intuition. We chose a double ring oscillator consisting of a Main PLL and a Dither PLL as example to demonstrate how such systematic methodology can even handle large circuits